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Intel ditches the monolithic chip on its way back to the top
Intel’s efforts to catch up with Samsung and TSMC coincide with a shift away from monolithic silicon toward disaggregating functions into multi-chip packages.
Initially, Moore’s law was principally powered by geometric scaling. Then, about fifteen years ago, chip manufacturers turned to new materials and device structures to keep it going. More recently, design technology co-optimization (DTCO) techniques have been added to keep squeezing more performance and density gains out of silicon. And pretty soon, all aspects of an entire IC-based system will need to be co-optimized, even taking into account what tasks that system needs to perform.
Of all the ways to improve IC performance, system technology co-optimization (STCO) will make the biggest difference, Ann Kelleher, head of technology development at Intel, told at this year’s International Electron Device Meeting (IEDM) in San Francisco. Kelleher’s views on the importance of system scaling echo those previously expressed by other semiconductor industry figureheads, including ASML’s Martin van den Brink and TSMC’s Mark Liu, but it’s interesting to take a closer look. After all, Intel is playing catch-up to Samsung and TSMC, and STCO may be a key element in getting back on top.