Imec shows progress in CFET development

Imec has demonstrated for the first time electrically functional complementary FET (CFET) devices with stacked bottom and top source/drain contacts. The transistor architecture consisting of nFETs and pFETs stacked on top of each other was integrated at 18nm gate length, 60nm gate pitch and 50nm vertical separation between n and p devices. Electrical functionality was demonstrated on a test vehicle with nFET and pFET devices using a common gate and top and bottom contacts connected from the front side.

“When developing the bottom contacts from the front side, we encountered multiple challenges, affecting bottom contact resistance and limiting the process window for top device source/drain formation. At the 2024 VLSI Symposium, we show that it’s feasible to move the bottom contact formation to the wafer backside, despite additional process steps linked to wafer bonding and thinning. The top device survival rate increased from 11 to 79 percent, making backside bottom contact formation an attractive option for industry. Research is currently ongoing to identify the optimal contact routing approach,” says Naoto Horiguchi, director CMOS device technology at Imec.

The next-generation transistor architecture is scheduled for introduction at the A7 node at the earliest.