Samsung prepares for 3D DRAM

Paul van Gerven
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Samsung is planning to introduce vertical-channel transistors into DRAM in the second half of the decade, and subsequently move to stacked DRAM beyond 2030. The memory maker revealed its plans at the Memcon event held 26 and 27 March in California. A slide showing Samsung’s next-gen DRAM roadmap was published by Semiengineering.

Source: Semiengineering.com

Introducing ‘vertical’, FinFET-like transistors in DRAM is said to allow the use of a more efficient cell design called 4F2. “This layout allows a shrink of the chip area by approximately 30 percent compared to existing 6F2 structures, without requiring smaller lithography nodes,” wrote Simone Bertolazzi, Principal Analyst Memory at Yole Group, earlier this year.

Unlike NAND producers, DRAM manufacturers have held off from 3D architectures due to the more complex nature of DRAM and the associated manufacturing process. At some point, however, stacking layers will be the last option to keep scaling DRAM. 3D DRAM may also offer performance and power consumption increases.

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