Data is increasingly influencing ASML’s activities. Digital technologies are now essential to keep wafer fabs humming with profitable yields, but for ASML, the underlying knowledge and instruments also translate into growing business opportunities.
ASML is a seasoned hardware company – built on physics, built by physicists. Litho equipment is still the major moneymaker, accounting for 70 to 80 percent of its revenue. But in the past twenty years, the company has been very diligently adding computational technology and measuring systems to support its steppers and scanners. Data and software are now heavily impacting ASML’s research and development. It might be gushy to state that without metrology, data, number crunching and correction loops, the newest litho technology can’t produce a single die. It’s certainly fair to say that without it, chip manufacturers can’t achieve the yields that are needed for a profitable semiconductor business.
It all started in 1999 with the acquisition of Masktools, a company of only ten employees that worked on technology for mask optimization. The latest gain in this hunt is Hermes Microvision (HMI), at the time of the 2.75-billion-euro acquisition in 2016 a 350-employee Taiwanese supplier of e-beam pattern verification systems (link in Dutch). According to ASML, HMI has now doubled its headcount – also thanks to the takeover of the experts from the Dutch e-beam litho company Mapper, which went broke late 2018 (link in Dutch).
Digital technology and data are getting more crucial to produce chips. Not surprisingly this means business. The potential is so big that ASML is addressing it with a special business line: applications. This activity covers computational lithography, optical and e-beam metrology, process control software and e-beam inspection. At ASML’s recent investor day, Jim Koonmen, EVP Applications Business, pointed out that he expects his business to grow at an average yearly rate of around 15 percent “all the way up through 2025”.
That means ASML is set on a course to win more than half of its total addressable market for applications – expected to be 5.5 billion euros in 2025. If the litho giant succeeds, it can expect to make more revenue that year with metrology, tooling and data-related business than its total revenue in steppers and scanners was around ten years ago.
ASML is no longer hiding that with this strategy, it’s on a head-on collision course with KLA, up to now the biggest metrology supplier in the semicon industry. The tooling and products around metrology allow the Dutch company to significantly improve the overall litho performance. Computational litho is able to simulate the whole pattern formation in the scanner. Sensor data, number crunching and machine learning algorithms all help optimize the scanner setup for a larger process window: the whole chip fabrication process becomes less vulnerable to process variation. Fab processes like deposition and etching may vary or even go off-limit and endanger yield but litho can correct and compensate for this.
Processed wafers are being measured and metrology instruments gather detailed information from all places in the fab: from inside the litho system but also between different process steps. In the past, ASML focused primarily on the chip details, now it is keeping an eye on the whole manufacturing process and is actually taking a growing responsibility for the economics of the whole wafer fab.
Litho is a very efficient process of printing lines and spaces but at the 32nm node, it became impossible to create a working chip only with lines and spaces in a single optical 193 nm laser scan. To be able to keep on shrinking advanced structures, chip manufacturers needed more exposure steps in a process called double or triple patterning. This is a critical procedure where lines are printed and cut with second or third exposures to make the needed circuitry.
This is adding complexity. More exposures for the most critical layers result in even higher requirements for finetuning patterns. The problem is that after every exposure, the wafer has to be processed in the fab and after numerous operations, it is reloaded into the scanner, increasing the error probabilities. “By reloading and re-exposing the wafers, you have to deal with uncertainty,” explained ASML’s CTO Martin van den Brink at the company’s Investor Day last year. He compared the process to precision surgery where both the size of the knife (critical dimension control), as well as its position (overlay control) matter.
“Like everything in life when you start using knives”, a grinning Van den Brink said, “you need to only cut where you intend to cut and not damage the good parts.” In litho surgery, this results in a tolerance for the cut, as well as for the surrounding area. “If you shrink, you need to drive down the whole envelope,” clarified Van den Brink. “Our whole holistic approach is focused on driving down the tolerance of this whole process.”
Precision surgery in chip litho is here to stay. In the advanced nodes, EUV will give some relief but soon enough that will also need double patterning to keep the semiconductor industry moving ahead.
Margin of errors
In those advanced nodes, the edges of the lines printed on chips are actually never straight. With smaller features, line edge roughness has more impact on the required overlay (the precision needed to stack patterns of subsequent exposures). This finetuning is increasingly important now that the overlay specifications are reaching the sub-2-nanometer domain.
Together, overlay and the uniformity and precision of the printed pattern form what litho experts call the edge placement error (EPE) budget. This is the patterning margin of errors in advanced nodes where overlay and feature size affect each other. The whole game of shrinking details and keeping the yield high is focused on the EPE budget.
In a presentation at last year’s investor day, Jim Koonmen showed a historic graph that pointed out ASML’s growing influence over processes in the fab that determine the EPE phenomenon. Back in 2005, the company’s product portfolio – at that time primarily consisting of scanners – addressed half of the EPE budget. Seven years later, after adding computational litho and mask correction technology with the acquisition of Brion and the development of its optical metrology platform Yieldstar, ASML was able to control 75 percent of the EPE parameters. Next year, when the chip industry expects to arrive at the 5nm node, the litho company expects to extend its influence on the EPE budget to 90 percent with advanced scanner actuators, process control software, HMI’s e-beam metrology and inspection, the use of Yieldstar and e-beam for gathering post-etch information.
Having a suite of products that’s able to address almost all of the customer’s edge placement error requirements is significant value, Koonmen pointed out to analysts last November: “The EPE is what really controls their yield in the fab. This is what controls their patterning performance.” Van den Brink added: “The market trends come back in our products and machine learning becomes a major part of the advancement.”