The end of traditional scaling is in sight, but Moore’s law thunders on. Imec’s Eric Beyne highlights one part of the bag of tricks that will open in the coming years: backside power delivery.
Those of us not yet retired are going to witness it with great certainty: the end of chip scaling as we know it with the current lithography tools. In roughly a decade, we’ll end up in sub-nanometer structures. The discussion about the lithography tool at that time – high NA, hyper NA or some other turbo variant of EUV – won’t really matter. The semiconductor industry will opt for the cheapest path to continue to make progress and manufacture chips reliably and quickly. Whatever tools IC process engineers will use, we’re going to feel the physical limits in the coming ten years.
The interesting thing is that everyone in semicon seems to agree that Moore’s law will continue for a while after that. The semiconductor roadmap is truly bursting with technology as well as ideas to keep up the steady rhythm of more devices on the same chip surface. System architects will use the available silicon surface more efficiently. They already have techniques at their disposal to guarantee atomic sharpness and exploit the third dimension.
Last summer at the 2022 IEEE VLSI Symposium on Technology and Circuits, Imec gave an insight into one of the techniques that will help chip architects continue to scale in the coming years: backside power delivery. Bits&Chips went to visit Leuven for an update from Eric Beyne.
Beyne has led Imec’s research into back-end chip technology for decades. That precisely his group is pulling a project that will have a strong impact on front-end architectures shows that the boundaries between back-end (packaging) and front-end chip fabrication (wafer processes) are blurring. Two hundred researchers from 45 chip manufacturers and equipment builders are currently involved in the development of backside power delivery at Imec.
Turning the power supply on its head
Simply put, chips consist of a substrate of silicon with a layer of active components, the transistors. Above that active layer lies a tangle of wires in a matrix of insulating silicon oxide. This wiring network serves two purposes: signaling and power supply. “Putting all that into the same surface is becoming increasingly difficult,” says Beyne, summarizing the key driver for backside power delivery (BSP).
The advancing scaling especially makes it increasingly difficult to get the right power to the active parts, the transistors. It’s a balancing act: the power consumption shouldn’t be too high, but the voltage must be high enough to switch. The problem is that the power wires aren’t only getting longer but also thinner.
The whole idea behind BSP is to turn that power supply on its head and offer the energy to the transistors from the bottom rather than the top. Hence the name, backside power delivery.
In the future, a chip with BSP will be made in two phases. First the chip with the active layer and the signaling above, then the backside power delivery. Once the active layer of microelectronics is processed, almost all of the silicon under it is removed. After that, work starts on the microelectronics network at the bottom.
Voltage and neutral wires
That removal of the carrier material is quite rigorous: almost the entire original wafer disappears. After sanding, polishing and etching, a layer of roughly 100 nanometers remains. Beyne: “This brings you right under the circuits. You can then connect at the level of the standard cells.” Standard cells are the basic blocks of the integrated circuit. They consist of multiple transistors and have simple functions such as addition and subtraction.
In June, Imec proposed to power these elementary building blocks in the 2nm chip generation via buried power rails – parallel power paths of alternating voltage and neutral wires. The distance between these buried power rails is around 200 nanometers for the most advanced chips but will move toward 100 nanometers in the future. With backside power delivery, the idea is to deliver the supply voltage and clock through the back – or if you prefer, the bottom – to these buried power rails.
The operation initially simplifies the routing scheme – the wiring above the transistors. It decouples the power supply and signaling between standard cells. At the same time, this modification allows the transistors in the chip architecture at the physical micro and nano level to be placed closer together.
Fourteen metal layers
With each chip generation, the complexity of the routing scheme grows. More and more metal layers are needed, and each additional layer means additional costs. To give an idea, TSMC produces its 7nm logic circuits with as many as fourteen metal layers. With the decoupling of power supply and signaling, that can come down, though of course there’s an added cost for the operations required to connect power to the backplane. After all, sanding, polishing and etching an entire wafer is quite rigorous.
But there are quite a few benefits. To get power at the transistor level, the current on today’s chips must pass through a lot of metal layers. The metal wires for the power supply have to be as wide and thick as possible to achieve low resistance. It goes from wide lanes above to thinner wires closer to the transistors. Especially the resistance of the latter lines is problematically high.
Beyne says the resulting voltage drop is causing more and more headaches for chip designers. “The power supply has to get down to the transistors via a spaghetti network. Because of the high voltage drop, 0.7 volts is no longer 0.7 volts at the transistor. The resistance is too high. Too low a voltage leads to missing clock cycles and thus mistakes. The critical path must be fast enough to switch within one clock period. That increasingly depends on the power supply of the transistor.”
Connecting power and clock directly
However, the higher the voltage, the higher the power consumption (which increases quadratically with voltage). “At some point, there’s no improvement to be made there,” Beyne says. “If you can connect the power and clock directly to the power arrays, the resistance is much lower. On the back end, only the connections are small at the level of standard cells. After that, you can go directly to wide metal layers and thus to a resistance that’s an order of magnitude lower.”
The distance between the buried power rails is now 200 nanometers and will go to 100 nanometers in future chip generations. Like FinFET transistors, these rails are vertical. “We’re going to connect them through a silicon layer of 100 nanometers. The holes needed for that have a diameter of 90 nanometers, of which we need 10 nanometers for the insulation. With that connection to the buried power rail, you have a direct line between the power supply and the transistor.”
Operations such as sanding away virtually all material from an 800-micrometer-thick silicon wafer are risky. The process needs to be controlled well. The roughest sanding can be done with an accuracy of 2 microns, according to Beyne. “After that, you remove extra silicon with a selective etchant, for which both dry and wet techniques are available.”
Silicon germanium or silicon oxide
The barrier layer where the etching must stop can be silicon germanium or silicon oxide, for example. SiGe can be applied with an epitaxy step, before putting on the transistors. Slices with a silicon oxide layer can be purchased as standard, called silicon on insulator (SOI) wafers. The selectivity of the etchants between the wafer silicon and the barrier’s silicon germanium or silicon oxide is one in a hundred. “So if you need to etch half a micron, and you over-etch 500 nanometers of silicon, you only lose 5 nanometers of the barrier material.”
High-end chips require billions of connections, called through-silicon vias (TSVs). “There are a lot of them so the current through the last narrow connection is very low.” Back-end wiring doesn’t require advanced lithography. “In front-end lithography, 90 nanometers is mature.”
But that doesn’t mean that laying out billions of TSVs is a simple job. Beyne: “It would be simple if the wafers wouldn’t deform. But if you bond two wafers, you also have to deal with the deformation of the wafer during bonding. That’s a specific problem that occurs with all wafer processing, just as a sticker stretches when you put it on. You have to deal not only with rotational translations but also with stretching and other deformations.”
Correction in lithography
The solution must come from the lithographic equipment. These have ample opportunities for correction. “An ASML system is equipped to make third-order corrections to the projected image. The remaining layer of 100 nanometers (after sanding and etching, RR) is transparent, so you can also see the alignment markers from the back. With the correction, we achieve 10-nanometer accuracy, so you can land such a 90-nanometer-wide TSV properly on a buried power rail and not on the transistors next to it – that’s actually the big challenge.”
Intel, meanwhile, has announced backside power delivery under the name “Powervia.” The US chip company will introduce the technology in its 20A chips (Intel uses angstroms instead of nanometers for its upcoming generations). 20A will hit the market in 2024 or 2025.
For BPD, the entire industry needs to prepare, including chip design tool vendors. “EDA tools need to understand that there are connections in the basement of the chip rather than in the attic.” But all major semiconductor companies are exploring the technology, although Samsung and TSMC haven’t yet made public their exact plans.