Paul van Gerven
27 October 2021

Improving semiconductor technology may require a more eclectic approach these days, but shrinking chip structures remains a staple in the industry’s scaling efforts.

“Over the past 15 years, our industry has achieved about 2x energy-efficient performance improvement per 2 years. System performance and energy efficiency will continue to advance at this historical rate,” TSMC chair Mark Liu predicted in his keynote lecture at the 2021 ISSCC. As he was saying the words, the slide on display showed the historical trend being extrapolated to 2040. Almost two more decades for this alternative version of Moore’s Law – that’s quite the statement.

Energy-efficient performance (EEP) is the number of operations a chip performs per second divided by the energy expended per operation. This metric has been proposed to replace raw computing power as a measure of chip performance progress, which stalled around 2006, when Dennard scaling broke down.

ASML system scaling
Until the mid-00s, improvements in chip technology were mostly the result of shrinking chip structures. When Dennard scaling broke down, scaling became a more eclectic, system-based game. Source: ASML

Robert Dennard and colleagues postulated in 1974 that as transistors get smaller, their power density stays constant. This allowed chipmakers to raise clock frequencies – and therefore performance – from one generation to the next without significantly increasing overall circuit power consumption. Dennard scaling, however, ignored leakage currents and threshold voltages, which started to cause thermal issues in the mid-00s. This resulted in a stagnation of the clock frequency, prompting the need for another metric to measure progress in chip technology.

In the Dennard era, EEP on the transistor level quadrupled every two years, CTO Martin van den Brink showed at ASML’s recent investor event. From then on, continued dimensional scaling kept things moving forward, but the stalled clock frequency caused the transistor-level EEP gains to slow down.


So, isn’t that the beginning of the end of Moore’s Law? Not quite, because there’s more to advancing semiconductor technology than decreasing component dimensions. There’s also scaling on a device level, which involves new transistor designs, perhaps incorporating new materials. On a circuit level, design optimization techniques add to intrinsic scaling to increase logic density. Liu showed that design technology co-optimization (DTCO) may be responsible for as much as half of the density increase at the 3nm node.

Beyond the component, chip and circuit level, integrating multiple dies or chips in a single package does more than just increasing transistor count: it can provide speed improvements and power reductions. Tight integration of logic and memory, for example, will boost overall performance. And when combining different chips, each can be optimized for a specific task, improving overall efficiency.

Thus, traditional ‘monolithic’ scaling makes way for a more eclectic approach to scaling on a system level. In fact, Moore’s Law already made this evolutionary step fifteen years ago. This is the reason why EEP gains slowed down on the transistor level but not on the system level. System EEP hasn’t managed to keep with the historical 4x increase per 2 years since 2005, but innovations such as multicore and high-k materials have kept the progress rate at a healthy 3x/2 years (Liu’s 2x/2 years was a little modest, according to ASML).

Van den Brink said he “doesn’t have the guts” to predict that the semiconductor industry will stick to this pace all the way to 2040, as Liu did, but he thinks it should hold until 2030.

Error budgets

Nonetheless, shrinking chip structure dimensions will remain an essential part of getting Moore’s Law going. “Advancing transistor technology not only provides performance and energy efficiency gains but also the necessary headroom to add features and to innovate in architecture and applications software. It’s worth noting that without device density improvements, there would be insufficient on-chip cache, no energy-efficient multicore chips,” Liu explained at the ISSCC.

ASML litho roadmap
Expected metal pitch scaling doesn’t quite manage to keep up with a 2x dimension improvement every 6 years. Source: ASML

Van den Brink showed how customers want the metal pitch, which is the smallest pitch in logic chips, to shrink over the next decade. Lithographic parameters such as overlay and optical proximity correction (OPC) need to go down more aggressively than that to increase chipmakers’ error budgets. “Our roadmap is highly based on this projection,” the CTO said. ASML has its work cut out for itself for at least another decade.