René Raaijmakers
12 August

With the promise to make small series cheaper, the Japanese Minimal Fab delegation of AIST was welcomed with open arms in Nijmegen, but investors still have to sign on.

A Japanese as you rarely see them. Shiro Hara is bouncing in front of the screen as he presents his Minimal Fab concept at the Novio Tech Campus in Nijmegen. Shortly after the turn of the millennium, Hara came up with a concept for miniature chip factories at the Japanese National Institute for Advanced Industrial Science and Technology (AIST). With his Minimal Fab chip factories, he wants to substantially reduce the costs of small chip series. The required investments will also be small.

His Minimal Fab consists of modules that process small silicon slices as large as a 2 euro cents (0.5 inch, 12.5 mm) coin. An advanced cleanroom is not required. Each slice is in a sealed cassette, a miniature version of the FOUP transport containers in conventional fabs.

Shiro Hara presenting his Minimal Fab concept at the Novio Tech Campus in Nijmegen, last May.

During his visit to Nijmegen, Hara mainly made it clear that his concept makes small series of chips cheap. That’s precisely why the Business Cluster Semiconductors The Netherlands and Domicro hosted Hara and his delegation. “Such a concept is desperately needed to stimulate innovation in chip design and the use of chips in domains with small numbers,” says Barry Peet of BCSemi NL. He welcomes investments in a minifab in The Netherlands. “Producing chips in low numbers in a flexible, fast way and at low costs makes it possible for the Netherlands and Europe to stay ahead in various fields where we play a leading role, such as RF, MEMS and photonics. We’re happy to help get the Dutch and European semicon ecosystem involved.”

“The concept fits very well with current trends in the manufacturing of end products,” comments Sorin Stan, director of business development at VDL ETG and present at Hara’s presentation, last May. “The trend is towards customized products, small series, less waste and lower cost.” As positive aspects, Stan sees the standardization of wafer carriers, mask-free exposure and processing in closed modules as a result of which no cleanroom is required. He believes that Minimal Fab has a considerable chance of success, but he also notes that there are still significant challenges ahead at this early stage.

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Stan estimates that a company with sufficient interest and financial resources can get a first fully functional Minimal Fab operational within three years. “On the assumption that fundamental R&D is really done, and the fifteen to twenty basic modules that are needed are developed by AIST.”

Stan notes that the current tooling cannot produce more than 100-150 transistors per chip. He sees that as the weakest point, even though there is an aggressive roadmap to nanometer resolutions. “A simple but also marketable application such as a simple controller for IoT quickly uses a few thousand transistors,” explains Stan. MEMS applications are an alternative, but that’s a market with much fewer opportunities.