Paul van Gerven
18 November 2020

Despite having been introduced into volume production, EUV lithography still has some way to go. It will take up to three years before the technology reaches the same maturity level as DUV.

When TSMC introduced EUV lithography into high-volume semiconductor manufacturing last year, it did so cautiously. In a bid to reduce the usage of multipatterning, the so-called N7+ process featured up to four EUV-patterned layers. For its successor, the N5 node, that number goes up to a maximum of 14 layers. By mid-2022, when production of the 3nm node (N3) will get into full swing, over 20 layers per chip will be printed with an EUV scanner, ASML CEO Peter Wennink recently told investors (without mentioning TSMC specifically).

How is TSMC going to print all those layers? Well, installing a lot of machines is one way to go. Already, the Taiwanese foundry says that it has half of the world’s EUV tools in operation and according to Digitimes, the company just put in an order for 13 more. As fab floor space is extremely expensive, though, TSMC and other leading-edge chipmakers prefer to install as few EUV scanners as possible. They’d rather buy machines that process more wafers per hour, day or week.

Credit: ASML


This was true a year ago, and it still is today. “Give us more EUV wafers,” is what customers consistently keep asking, Wennink said. Ultimately, chipmakers would like to see the characteristics of EUV systems to match those of their much more mature DUV counterparts, while retaining their superior imaging capabilities, obviously.

ASML would be happy to oblige, but, as with any technology transition, this takes time. “The entire industry is climbing the maturity curve and that’s going to be there with us for the next one or two years before it really starts hitting home on maturity levels that we saw with DUV,” Wennink explained.

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By another metric, it might take a bit longer. In a video interview published on ASML’s website, CFO Roger Dassen said that EUV’s gross margin will start to approach that of DUV in two to three years. Gross margin is a good indicator of maturity because as soon as ASML’s EUV activities are as profitable as the DUV activities, it’s fair to say EUV has reached peak maturity. Until now, the less-than-desired productivity of EUV scanners meant that ASML has had to content itself with lower-than-company-average EUV gross margins. Every time a new model is launched, however, it creates more added value for customers, thus increasing profitability of the EUV activity (assuming cost is held in check).

Case in point, ASML recently launched a new model, the Twinscan NXE:3600D, which increases productivity by 18 percent to a maximum of 160 wafers per hour. According to Dassen, this and other improvements allow ASML to raise the tool’s selling price by 10-15 percent.


Clearly, though, there’s still some way to go before EUV scanners grind through 275+ wafers per hour like their DUV counterparts do. The same goes for uptime. Whereas DUV tools are routinely operational for 98 or 99 percent of the time, average EUV uptime currently hovers around 90 percent.

Incremental improvements in the system’s design will help to improve both throughput and uptime, as they have done before. For example, over the past year, ASML managed to speed up the swapping of the collector (the mirror in the EUV light source, which needs regular cleaning) and the refilling of the tin canister (tin droplets are ‘plasmatized’ to produce EUV light). And soon, it expects to introduce a new generation of pellicles that absorb less precious EUV light, increasing throughput for chipmakers that opt to use these mask-protecting membranes.

Additionally, as Wennink said, it’s a learning process, for both ASML and the entire industry. The longer EUV systems are operating in the field, the more opportunities will present themselves to optimize their engineering and utilization.