Paul van Gerven
10 July 2019

For the 3nm logic technology node, M2 interconnect layers with metal pitches as tight as 21 nm need to be manufactured while preserving the back-end-of-line’s performance. It’s by no means an easy task, but it appears Imec has it under control. This week, the Leuven research institution presented a 21 nm metal pitch test vehicle that shows a 30 percent improvement in RC delay compared to previous generations. It also performs well in terms of reliability.

To pattern the M2 layer, a hybrid lithography approach was proposed, using 193 nm immersion-based self-aligned quadruple patterning (SAQP) for printing the lines and trenches, and extreme ultraviolet lithography (EUV) for printing the block and via structures. The test vehicle implemented a barrier-less ruthenium (Ru) metallization scheme and an insulator with dielectric constant k = 3.0.

Credit: Imec