Imec has drawn up a roadmap that will take the semiconductor industry to the 2-angstrom (0.2nm) node in 2036. A combination of lithography-enabled dimensional scaling and increasingly complex transistor structures will take us there, says the Leuven-based research institute. From the next decade onward, n- and p-type switches will be stacked on top of each other in complementary FET circuits with a metal pitch of 16-12 nanometers (it’s 40 nanometers for the 7nm node). Eventually, these CFETs will incorporate atomically thin 2D materials such as tungsten disulfide.
At the system level, sub-2nm chips have to face up to the fact that memory bandwidth can’t keep up with processor performance. Imec proposes to bring processor and memory closer together, perhaps even stacking them on top of each other in a 3D system-on-chip package. This will speed up communication between cache memory and logic. To achieve extremely high bandwidth off-module connectivity, optical interconnects, integrated on photonics interposers, are being developed.
Another system-level challenge is getting enough power into the chip and the heat. Power distribution currently runs from the top of the wafer through more than ten metal layers to the transistor. Imec is working on a solution from the backside of the wafer. Power rails will sink into the wafer and be connected to the backside using nano-through-silicon vias in wider, less resistive materials. This approach will decouple the power delivery network from the signal network, improving the overall power delivery performance, reducing routing congestion and, ultimately, allowing further standard cell height scaling.
In the long term, Imec believes that the Von Neumann architecture needs an overhaul. “We’ll need to evolve toward domain-specific and application-dependent architectures, with massive parallelization comparable to the way our human brain works. This implies that the CPU will have a smaller role in favor of custom-made circuits for specific workloads.”