Paul van Gerven
27 February

Bigger masks would enable chipmakers to expose more wafer area in a single step, removing design constraints and possibly increasing throughput.

Intel is pushing bigger mask sizes for high-NA EUV lithography and perhaps even low-NA EUV, CEO Pat Gelsinger told the More than Moore blog. “I’m challenging both ASML and my mask-making team to get me to bigger mask sizes so we can get the field size back, and maybe even bigger mask sizes to get even more economics out of EUV overall.”

Mask size and field size, ie the wafer area being exposed in a single exposure step, are connected. The industry standard EUV field and mask sizes are 26 by 33 millimeters and 6 by 6 inches, respectively. To make high-NA work, ASML and Zeiss opted to double the magnification in one direction, resulting in a half-sized field of 26 by 16.5 millimeters. ASML has beefed up the wafer stages to make up for the loss in throughput, but printing larger die sizes with half-sized fields still faces constraints, since images will have to be ‘stitched’ together to create full-sized chips. Going back to the industry standard mask size might also increase throughput.

The field size can be restored to full by doubling the mask size (6 by 12 inches). Initially, this option was rejected by the industry on the basis that it’s more cost-effective to keep the existing EUV mask infrastructure. Now, Intel – as the most enthusiastic supporter of high-NA EUV – wants to reopen that discussion.

ASML high NA cleanroom Veldhoven 069
Credit: ASML

Moore’s Law

Of course, a step up in size is far from trivial. It will be challenging to produce even larger defect-free mask blanks and pellicles. Equipment to manufacture, inspect and handle masks will have to support the new size. ASML will have to contend with a bigger and heavier reticle stage.

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The supply chain will only be prepared to make the necessary investments if there’s a reasonable expectation of a return. This requires support from all leading-edge chipmakers, and so far, Samsung and TSMC have been mum on the matter. ASML is agnostic. A spokesperson told Bits&Chips that the equipment manufacturer would support the development of bigger masks if prompted by the industry.

Gelsinger said that even without changes to the mask size, high-NA will be cost-effective for Intel. “We’ve looked at it pretty carefully – when you go to double patterning with low-NA versus single patterning with high-NA. We can make the economics work.” In fact, Gelsinger is counting on high-NA to restore the economics of Moore’s Law. “It’s not just building faster transistors, lower-power transistors, but cheaper transistors as well. That’s a big priority for us.”