Paul van Gerven
10 July 2019

At Semicon West in San Francisco this week, Intel shared new details about and ambitions for its advanced chip packaging program. “Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip. A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors,” said Babak Sabi, Intel corporate vice president Assembly and Test Technology Development.

Last year, Intel revealed (link in Dutch) the Embedded Multi-die Interconnect Bridge (EMIB), which is used to flexibly link up heterogeneous chips into so-called 2.5D chip packages. It also showed off the Foveros architecture, in which dies with different functionalities are stacked into a single chip package, ie a 3D IC.

This week, Intel presented a combination of EMIB and Foveros: interconnecting two or more Foveros packages side by side into an even more advanced package. In addition, the company unveiled a new interconnect technology called Omni-Directional Interconnect. ODI, among other things, allows vertical communication between stacked chiplets using through-silicon vias as well as horizontal communication between top chips.

Intel Foveros EMIB_web
Combining EMIB and Foveros into a 3D IC. Credit: Intel