From a cryogenic CMOS controller for quantum computers to an ultra-low-power transceiver for ingestible electronics pills – our small corner of the globe again came up with a lot of top-notch IC design.
The International Solid-State Circuit Conference (ISSCC) is a mecca for the international IC design community – both from academia and industry. Getting a paper accepted is the highest honor that can be bestowed on an chip designer. This year’s edition, held 16-20 February in San Francisco, featured eight papers from researchers working at Dutch universities (seven from Delft and one from Twente), one from NXP (and another one in collaboration with Delft) and five from Imec (including Imec Netherlands, which participates in Holst Centre).
We asked the honorees about their work. NXP, unfortunately, was unable to contribute.
Delft University of Technology
The world’s first cryo-CMOS controller for spin and superconducting qubits
Paper: A scalable cryo-CMOS 2-to-20 GHz digitally intensive controller for 4×32 frequency multiplexed spin qubits/transmons in 22nm FinFET technology for quantum computers
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Researchers: Bishnu Patra, Jeroen van Dijk, Edoardo Charbon, Fabio Sebastiano and Masoud Babaie
Collaborators: EPFL, Intel, TNO
What is your paper about? What did you design?
The paper proposes Horse Ridge, the first cryo-CMOS controller IC for spin and superconducting qubits, the core computational units of quantum computers. Cryo-CMOS means that the CMOS IC operates at cryogenic temperatures, in this case 3 kelvin (-270 degrees Celsius). This means that the controller can be placed inside the cryogenic vessel of the quantum computer where the qubits reside. This in turn enables unprecedented levels of miniaturization, paving the way for scalable architectures that can handle larger and larger number of qubits – which are required to make quantum computers practical.
What applications could it be used for?
All quantum devices requiring a very precise arbitrary waveform with gigahertz frequencies and extremely precise phase and amplitude control can benefit from Horse Ridge. Quantum computing is the main application, obviously, but new applications in quantum communications and quantum sensing are also expected to emerge.
Why is it superior to previous designs?
This design achieves a much larger number of channels than previously achieved, ie it can control many more qubits simultaneously. In addition, Horse Ridge has a very sophisticated way of suppressing interference between qubit controls, thereby allowing for more reliable control of a larger number of qubits. Finally, the chip has a rich micro-instruction set, thus enabling easy programming of qubit operations from a higher level of the quantum stack.
Why is this contribution ISSCC worthy?
It was selected because of the compelling architecture based on digitally-intensive design with a clear roadmap for extension in the near to medium term to achieve scalable quantum computers thanks to localized qubit control at cryogenic temperatures. In addition, the performance of the chip and its design for use at 3 K was a strong argument in favor of presenting the work at the conference in an all-quantum session. This trend, with a second keynote speech on quantum computing in three years, attests to the growing interest of the solid-state IC community in quantum-related problems.
A most versatile cryogenic oscillator
Paper: A 200 dB FoM 4-to-5 GHz cryogenic oscillator with an automatic common-mode resonance calibration for quantum computing applications
Researchers: Jiang Gong, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon
Collaborators: EPFL, Intel
What is your paper about? What did you design?
We proposed a digital calibration loop that automatically adjusts the oscillator common-mode resonance at twice the oscillation frequency to ensure that the oscillator always operates near its optimum performance. This technique suppresses the oscillator phase noise at 100 kHz offset frequency by more than 10 dB over the temperature range from 4-300 K.
What applications could it be used for?
The proposed calibration is a general technique to reduce the oscillator phase noise. Consequently, its applications are broad, ranging from wireless communications to quantum computing, where low-power and high-accuracy frequency generation is required.
Why is it superior to previous designs?
Our design simultaneously achieves lower phase noise and lower power consumption compared with the state of the art. It’s enabled by a digital calibration technique, which ensures that the oscillator’s capacitor configuration is optimal. Furthermore, the proposed circuit dramatically reduces the design costs and time-to-market since any off-chip factory-level calibration is avoided.
Why is this contribution ISSCC worthy?
This work will enable the realization of cryogenic low-power low-jitter frequency synthesizers required for the control and read-out of quantum bits. Additionally, RF oscillators are the heart of any communication system. Our digital calibration automatically adjusts the oscillator configuration such that the oscillator operates near its optimum performance across different process, voltage and temperature variations.
An RC frequency reference with quartz-like accuracy
Paper: A 16 MHz CMOS RC frequency reference with ±400 ppm inaccuracy from -45 °C to 85 °C after digital linear temperature compensation
Presenters, group leader: Cagri Gurleyuk and Sining Pan, Kofi Makinwa
Collaborator: Infineon
What is your paper about? What did you design?
Our paper describes a CMOS frequency reference that achieves high accuracy about 400 ppm around its nominal 16 MHz output frequency after an industrially feasible two-temperature trim. Since most of the remaining error is systematic, this can be reduced to below 100 ppm with the help of a one-time batch calibration. The frequency reference works by locking an inaccurate ring oscillator to the well-defined time constant of an RC filter. A high-resolution resistor-based temperature sensor then compensates for the filter’s residual temperature dependence.
What applications could it be used for?
All communication standards require a frequency reference. Our work allows wired communication standards such as CAN or LIN to be fully realized in a system-on-chip, obviating the need for external quartz or MEMS oscillators. This is industrially attractive because it reduces component count and board area, thus reducing manufacturing cost.
Why is it superior to previous designs?
It achieves best-in-class accuracy, over a statistically relevant number of samples and over multiple batches. Also, while previous designs relied on expensive multi-temperature calibration, our work only requires a simple two-point calibration, which can be combined with a one-time batch calibration if more accuracy is required.
Why is this contribution ISSCC worthy?
Our design achieves the best reported accuracy for an RC-based frequency reference and as such, it will be a benchmark for future designs. It’s also the first one that does this with an industrially feasible calibration methodology and with low area and power dissipation.
An amplifier for better ultrasound images of the heart
Paper: A 2 pA/√Hz transimpedance amplifier for miniature ultrasound probes with 36 dB continuous time-gain compensation
Presenters, group leader: Eunchul Kang and Mingliang Tan, Michiel Pertijs
Collaborator: Vermon
What is your paper about? What did you design?
Our paper describes a low-noise amplifier of which the gain can be smoothly varied over a 40 dB range. The amplifier is designed for integration in a miniature ultrasound probe, in which it’s responsible for amplifying the received echo signals from which the ultrasound images are reconstructed. It compensates for the decaying amplitude of the received echoes with time, thus saving substantial power by relaxing the dynamic range requirements of the rest of the receive chain.
What applications could it be used for?
Our design is intended for use in miniature ultrasound probes, such as intra-cardiac imaging catheters, in which many tiny transducer elements emit sound waves and receive echo signals to make a real-time image of the body. Together with our collaborators from Vermon, a leading manufacturer of ultrasound probes, we incorporated the new amplifier into a prototype of a 64-element intra-cardiac imaging probe.
Why is it superior to previous designs?
The presented amplifier is unique in that it provides continuous smooth gain control, leading to improved image quality compared to earlier designs that use discrete gain steps. With a chip area of only 0.12 mm2, the presented amplifier is small enough to be integrated directly underneath a transducer element. The realized functionality was previously only available in amplifiers used in ultrasound imaging systems, which are too large to be integrated in a miniature probe and consume far more power. Our low consumption of about 5 mW per amplifier is crucial in probes that operate within the human body, since their power consumption needs to be minimized to avoid overheating.
Why is this contribution ISSCC worthy?
The presented amplifier employs a new circuit topology consisting of a capacitive ladder feedback network and a current-steering circuit to obtain an accurate linear-in-dB variable gain. It’s the first time that this functionality is reported in a design that’s suitable for integration into a miniature probe. We’ve integrated the amplifier in a 64-channel ultrasound transceiver ASIC and combined this with a CMUT transducer array in a prototype catheter-based intra-cardiac probe. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the amplifier scheme.
University of Twente
An IoT design Don Quixote wouldn’t be able to resist
Paper: A 370 μW 5.5 dB-NF BLE/BT5.0/IEEE 802.15.4-compliant receiver with >63 dB adjacent channel rejection at >2 channels offset in 22nm FDSOI
Researchers: Bart Thijssen, Eric Klumperink, Philip Quinlan, Bram Nauta
Collaborator: Analog Devices
What is your paper about? What did you design?
We presented a 2.4 GHz multi-standard Internet-of-Things (IoT) wireless receiver fabricated in 22nm FDSOI. The receiver can be used for multiple IoT applications such as Bluetooth Low Energy (BLE) and Zigbee. In addition to careful design across the entire receive chain, we included two main innovations: an analog finite-impulse-response (FIR) filter and a novel frequency divider architecture.
The analog FIR filter acts as channel selection filter and improves the receiver’s blocker resilience. This analog implementation of a conventional digital filter allows for very strong filtering while also reducing the power consumption. Furthermore, the requirements on a subsequent analog-to-digital converter (ADC) can be relaxed without compromising flexibility.
Our wireless receiver requires 25 percent duty-cycle clock phases at 2.4 GHz to downconvert the received RF signal and convert this signal to bits. The standard approach is to divide a differential 4.8 GHz clock signal by two to create four 25 percent duty-cycle phases at 2.4 GHz. We invented a novel frequency divider architecture to accomplish this with reduced power consumption. We named it the “Windmill divider”, after its architecture and the rotating nature of the outputs. In contrast to prior art, the Windmill divider contains only a single gate between the local oscillator input (LO+/LO-) and the 25 percent duty-cycle outputs (Qx, x = 1..4). In this way, we combine a very low-power consumption (41 µW) with low phase noise and mismatch.
What applications could it be used for?
Our design can be used in a wide range of IoT devices, such as wireless earbuds, smartwatches and sensor networks, as well as wireless devices such as keyboards and mice.
Why is it superior to previous designs?
The analog FIR filter makes the receiver over one hundred times more blocker resilient than state-of-the-art designs, which means that the receiver will hold its own in an increasingly crowded wireless environment. On top of that, the total power consumption of the receiver is 370 µW, which is more than two times lower than prior art.
Why is this contribution ISSCC worthy?
Thanks to several innovations, we achieved unprecedented performance combined with ultra-low power consumption – making our design very relevant for the semiconductor industry. As recognition for this work, Bart Thijssen received the Analog Devices Outstanding Student Designer Award – making him the European designer to receive this award.
Imec
First millimeter-scale wireless transceiver for electronic pills
Paper: A 3.5 × 3.8 mm crystal-less MICS transceiver featuring coverages of ±160 ppm carrier frequency offset and 4.8-VSWR antenna impedance for insertable smart pills
Presenter, group leader: Minyoung Song, Christian Bachmann
Collaborator: University College Dublin
What is your paper about? What did you design?
Imec presented the first fully-integrated mm-scale wireless transceiver for smart insertable pills. The wireless transceiver is implemented in 40nm CMOS and includes an on-chip tunable matching network (TMN) that enables a miniature 400 MHz antenna, and as such avoids external and bulky matching components.
What applications could it be used for?
Autonomous ingestible sensors can measure health parameters such as gut health and transmit in real time the data outside the body. Compared to current procedures like endoscopic inspection and stool sample analysis, this new type of health tracker will make diagnoses of digestive processes and gastrointestinal diseases more comfortable for patients while collecting information over a longer period of time.
Why is it superior to previous designs?
One of the challenges in realizing electronic pills is developing a wireless link that meets the volume, power and performance constraints for reliable data transmission during the period of time that the sensor is collecting data inside the body. Imec’s new wireless transceiver supports the medical 400 MHz frequency bands such as MICS (Medical Implant Communication Service), MEDS (Medical Data Service) or Medradio (Medical Device Radiocommunications Service). The whole transceiver module including antenna occupies a volume of less than 55 mm3, which is up to thirty times smaller than state-of-the-art devices. The whole wireless module occupies an area of 3.5 by 15 mm2, including a 3.5 by 3.8 mm2 PCB and a miniature 400 MHz antenna.
The small form factor is realized thanks to a new crystal-free transceiver architecture, alleviating the need for an off-chip crystal device, and a 2 mm2 transceiver IC with the on-chip TMN. Small area is further achieved by a TX/RX shared matching network with only one on-chip inductor and a single-branch phase-tracking RX.
Why is this contribution ISSCC worthy?
It’s a first breakthrough in realizing autonomous ingestible sensors that can measure health parameters such as gut health and transmit in real time the data outside the body.
Ultra-sensitive and low-power radar
Paper: A 12 mW 10 GHz FMCW PLL based on an integrating DAC with 90 kHz rms frequency error for 23 MHz/μs slope and 1.2 GHz chirp bandwidth
Presenter, group leader: Pratap Renukaswamy, Barend van Liempd
Collaborator: Vrije Universiteit Brussel
What is your paper about? What did you design?
A novel low-power and extremely accurate phase-locked loop (PLL) for frequency-modulated continuous-wave (FMCW) radars. The radar RF front-end is fully integrated in a 28nm CMOS chip.
What applications could it be used for?
This PLL will be the key building block for a millimeter-wave motion detection radar at 60 GHz. It can detect movements, recognize gestures and even measure someone’s heartbeat.
Why is it superior to previous designs?
In order to accurately determine the distance and velocity of a target using a FMCW radar, you need a PLL that generates fast and highly linear chirps. You also need to reach a high modulation bandwidth, which determines the resolution of the radar. The big challenge was to design a PLL that meets all these conditions without consuming too much power.
We designed a PLL that achieves the performance targets while consuming only 12 mW power consumption. The PLL generates modulated waves centered around 10 GHz, the frequency of which increases by 1.2 GHz (or 12 percent) in just 51.2 microseconds. The linear increase of 23 MHz per microsecond has an uncertainty (rms-deviation) of 90 kHz. In its fastest mode, the same bandwidth is covered in only 12.8 microseconds with a rms frequency error of 168 kHz.
Why is this contribution ISSCC worthy?
This low-power PLL is a significant step in the development of a low-power 60 GHz radar, of which this PLL is a part. The transceiver details will be published later this year.