The transition to 5G is exciting but no small task given the degree of complexity at various points in the system. Multiphysics simulations simultaneously solve power, thermal, variability, timing, electromagnetics and reliability challenges across the spectrum of chip, package and system to promote first-time silicon and system success.
System-on-chips (SoCs) and radio frequency integrated circuits (RFICs) for 5G smartphones and networks need to manage huge amounts of antenna data and offer significantly high processing capabilities in thermally and power-constrained environments. The growing interdependence of various multiphysics effects like timing, power, electromagnetics, thermal and reliability in sub-16nm designs poses significant challenges for design closure. Traditional margin-driven, silo-based design approaches to the chip, package and board have limited simulation coverage and fail to unravel potential design weaknesses, causing field failures.
Multiphysics simulations simultaneously solve power, thermal, variability, timing, electromagnetics and reliability challenges across the spectrum of chip, package and system. Early analysis is key, but this comes with some requirements for SoC and intellectual property (IP) designs. The most important ones pertain to power efficiency, power integrity, reliability, advanced packaging and electromagnetic crosstalk.
The shift from 4G to 5G is expected to deliver a spike in cell edge data rates from 10 Mb/s to more than 1 Gb/s, plus a 50 percent gain in energy efficiency. For evolving generations of 5G implementations, the main focus is on predicting power profiling early in the chip design phases. Specific attention has to be paid to spectrum-related issues, traffic characteristics, radio interference and interoperability and network access-related issues.
Power efficiency is a key design consideration for 5G devices. Average power, peak power, peak change in power and sustained worst-case average power are all important for thermal robustness, power integrity and cost of system operation. Early feedback is critical to achieving 5G power targets.
For 5G SoCs, power grid signoff through traditional approaches isn’t feasible. This is due to severe routing constraints that can potentially cause timing convergence issues downstream. For advanced FinFET technology processes, the power grid’s node count is very high and any reduction in node count will affect accuracy. With very small design margins, power signoff solutions leave little margin for error. The slightest inaccuracy can result in product failure. It’s important, therefore, to analyze the entire power grid flat rather than partitioning the design with a “divide and conquer” approach.
Design for reliability is another key consideration for advanced SoCs used in 5G communication systems. These SoCs, for example, will be instrumental in enabling future mission-critical applications like self-driving cars. Reliability issues can be challenging at advanced FinFET nodes. FinFET designs have a high dynamic power density, and power directly impacts the chip’s thermal signature. Accurately modeling the temperature distribution on-chip by considering the chip in the context of the system is critical for ensuring its reliable operation.
Electrostatic discharge (ESD) design and verification are also becoming extremely challenging with the prominent use of IPs and high-speed interfaces in SoCs. ESD checks are now one of the key signoff metrics. Almost 55 percent of the failures are interconnect-related and can be avoided by performing systematic ESD checks during the design phase. But ESD protection that works at the IP level may not work at the SoC level due to poor connectivity to other IPs and circuits in the SoC. Therefore, it’s important to analyze the ESD protection schemes at the SoC level, across multiple voltage domains, to make sure they provide the intended low-resistance path for discharging a potential ESD event without stressing the functional devices.
Advanced packaging technologies will be the key driver of heterogeneous integrations in next-generation edge compute data centers and 5G electronics systems to achieve extreme performance, high system bandwidth, low power and low cost. The Internet of Everything – enabled by 5G infrastructure – will generate huge amounts of data to be processed and stored. The ability to handle such large volumes of data will be threatened by limited system bandwidth between the traditionally packaged processor and the memory integrated into the system.
Hence, advanced 2.5D/3D IC packaging technology will become a popular choice for 5G system designs. Short interconnection paths enabled by through-silicon vias between stacked chips lead to higher performance because of increased I/O speed. They also consume lower power because of their reduced capacitance and their smaller form factor due to the stacking of multiple dies. This is indeed a very promising technology, although it’s fraught with many challenges owing to its complexity.
Integrating a high-power beamforming module with sensitive analog and RF circuitry can lead to substrate noise propagation between the two, which can impact the overall performance. For accurate power noise analysis, it’s important for a designer to model the propagation of substrate noise in a dynamic voltage drop analysis. Integrating the digital beamforming module with sensitive analog and RF circuitry can cause switching noise to propagate through the substrate if insufficient isolation is guaranteed.
For reliable operation of the millimeter-wave RF module, it’s critical to have a methodology that allows for modeling of the substrate noise generated in a digital beamforming module using digital noise injection. The methodology also needs to perform analyses to determine the frequency and time-domain response of the analog/RF blocks.
For 5G, RF front-end circuits, high-performance reference oscillators and associated interconnects must be designed properly to ensure reliable operation at 6 GHz up to mm-wave frequencies. On-chip mixed-signal components are affected by electromagnetic effects and their design considerations should include self- and cross-coupling among various sensitive mixed-signal circuit blocks. Careful examination of the layout, parasitic inductance and capacitance, substrate modeling and trace resistance is critical for reliability. The need to model electromagnetic effects from DC up to mm-wave calls for special handling of layouts.