Paul van Gerven
5 April

A US-Dutch and a French partnership are betting on quantum computing to scale by piggybacking on CMOS infrastructure.

“The qubit systems we have today are a tremendous scientific achievement, but they take us no closer to having a quantum computer that can solve a problem that anybody cares about. It’s akin to trying to make today’s best smartphones using vacuum tubes from the early 1900s. You can put 100 tubes together and establish the principle that if you could somehow get 10 billion of them to work together in a coherent, seamless manner, you could achieve all kinds of miracles,” Sankar Das Sarma recently wrote in MIT Review.

What’s missing, the University of Maryland physicist continued, is a believable method of scaling. Just as modern electronics evolved from transistors to CPUs, quantum computing needs to take the number of qubits from handfuls to millions or even billions. Das Sarma asserts that this challenge tends to be underestimated, but a US-Dutch research team recently shared progress in building a scalable quantum computer. Another team from France presented a strategy to deliver a million qubits by 2024.

Unprecedented

Engineers from Intel and scientists from Qutech are betting on leveraging decades of semiconductor manufacturing experience to scale up quantum computing. Publishing in Nature Electronics, they showcase the first silicon qubit made in CMOS process technology.

For silicon qubits, nanometer-sized regions hosted at the interface of silicon and silicon dioxide are used to confine electron spins. These so-called quantum dots act more or less like atoms but are more practical to work with. After all, it’s easier to precisely position a quantum dot and arrange gates around it than to do the same with a single atom. In fact, the procedures to manufacture silicon quantum dots and conventional transistor structures are quite similar.

Qutech quantum CMOS
Credit: Qutech

Despite the similarities, however, it remained an open question whether silicon qubits can be manufactured in high yield within the confinements – ie design rules and processing options and conditions – of existing industrial semiconductor processing. For example, in research environments, e-beam lithography is the patterning technology of choice – a technique that’s not very popular in conventional IC manufacturing. Furthermore, common CMOS techniques such as chemical polishing were thought to be too harsh in producing quantum dots structures.

Intel and Qutech not only demonstrated the fabrication of a silicon qubits array on a 300-mm wafer using 193-nm immersion lithography and a full set of industrial processing techniques, but they also did so in high yield. “The device yield achieved by the Intel team was an unprecedented 98 percent, compared to 50 percent on a good day in our university cleanroom,” says Qutech lead scientist Lieven Vandersypen.

“So many articles state: semiconductor spin qubits in silicon are compatible with CMOS semiconductor manufacturing. But only now, we’ve proven that to be actually true,” he adds.

Complexity

French research outfit CEA-Leti and startup C12 Quantum Electronics also want to piggyback on CMOS infrastructure to scale quantum computers, but not by putting spins in silicon. Instead, the partners are planning to manufacture wafer-sized quantum chips based on carbon nanotubes.

Once considered to be a potential competitor to silicon, attempts to introduce carbon nanotubes into the realm of commercial electronics so far have failed. C12 thinks the nanostructures stand a better chance in quantum computing. “Silicon enabled the emergence of classical computing, it’s time for carbon to do the same for quantum,” the Paris-based company states on its website.

C12 carbon nanotube structure
C12’s carbon nanotube suspended above the gate electrodes. Credit: C12

C12 relies on ultrapure carbon nanotubes made exclusively from C12 carbon isotopes to suppress unwanted noise from nuclear-electron spin coupling, which can cause delicate quantum spin systems to collapse. Individual nanotubes are suspended above gate electrodes, which are used to form a double quantum dot structure within the tubes, trapping a single electron. This is the basis for C12’s qubits.

The concept of wafer-scale chips is unconventional but not entirely without commercial precedent. US startup Cerebras is marketing an AI and deep-learning chip so massive that only a single one fits on a 300-mm wafer. C12 is aiming at one wafer size smaller, ie 200-mm substrates.

Such extremely large chips can be ruined by a single defect on the wafer. Processing, therefore, needs to be flawless. Having demonstrated the ability to manufacture, with precision and in volume, core components to calibrate, control and read qubits using standard manufacturing processes, CEA and C12 believe they can make that happen. Mechanically assembling nanotubes onto CEA-fabricated chips through a proprietary process developed by C12, the partners claim they can produce a quantum electronic circuitry of near-arbitrary complexity.

CEA and C12 expect to demonstrate a prototype with as much as 1 million qubits in 2024. For comparison, IBM says it will cross the 1-million-qubit mark by the end of the decade.