After evaluating several process technology options for the 3nm node (N3), TSMC believes it has landed on a “very good solution”, CEO C.C. Wei told analysts in a conference call. As the foundry is still working with its lead customer to fill in the details, Wei did not give any specifics on the process. “We continue to work with our customer to define the spec, to define the approaches and to meet his requirement and are updating you about our choices next time,” he said.
Earlier this year Samsung announced it will take its N3 version into production in the second half of next year. Wei hinted these chips should be considered to be more or less on par with TSMC’s N5, which went into risk production a few months ago. Samsung, however, will employ performance-enhancing gate-all-around (GAA) transistors at N3, while TSMC stuck to FinFET structures at N5.
It remains unclear whether TSMC will move to GAA at N3 as well. “So far, in 5-nanometer geometry, FinFET is still the most competitive. For N3 we are evaluating everything,” Wei said. He added: “it’s very hard to switch the foundry. It’s very hard because the design board, the architecture, the design flow are all different.”
For N3 production ASML’s EUV scanners will be used extensively. TSMC first started using EUV for N7+ chips, but only for a few layers. N5 chips reportedly contain over ten EUV-patterned layers and it is very likely N3 will go even higher.
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