Paul van Gerven
23 August

Not costs or the arduous concurrent development of EUV lithography killed the 450-millimeter project, but competitive considerations.

A former TSMC executive has revealed why his company reversed its position on developing chip manufacturing processes on 450-millimeter wafers. In an interview with the Computer History Museum, former COO Chiang Shang-Yi says that in 2013, he advised CEO and founder Morris Chang, until then a warm supporter, to abandon the larger slabs of silicon. After careful consideration, Chang went along with Chiang’s suggestion, pulling a vital pillar out from under the project.

Chiang’s outpourings give more color to ASML’s decision to halt the development of 450-millimeter scanners (link in Dutch). As it now turns out, that decision followed a meeting at Semicon West in the summer of 2013, in which Chiang informed ASML, Intel and Samsung that TSMC’s priority was to develop advanced semiconductor – not 450-mm – technology.

Prior to that announcement, Bill Holt, Intel’s R&D and manufacturing boss, had made yet another impassioned plea for 450 mm – Intel had been the main driver of the wafer transition from the beginning. The implication wasn’t lost on Holt. “He was very upset and walked away. The following day, Intel announced that it was going to prioritize advanced technology development, and that was the end of the 450-millimeter wafer. Nobody has talked about it since,” Chiang says in the interview, of which a transcript has been published.

Squeeze-out

Chiang feared that TSMC would be crushed by Intel and Samsung if 450-mm wafers would become reality. That would essentially be a reversal of what had happened during the move from 200 to 300-millimeter wafers more than a decade earlier. At the time, that enabled the Taiwanese foundry to leave smaller competitors like UMC and SMIC behind for good. The same could happen to TSMC, at the time significantly smaller than Intel and Samsung, with another step in wafer size.

“Going to a bigger wafer size, people say it’s because of productivity. That’s not exactly true. It’s more like a game. It’s a game for the big guy to take advantage of the small guy. It’s pretty clear that’s the case. Why? Right now, if you want to go to 18 inch, the first thing that happens is that all the equipment vendors will produce their new equipment for 18 inch. They won’t make the most advanced technology for 12 inch. So the small players that don’t need 18 inch, they’re automatically out of the competition. So it’s the big guys squeezing out the small guys. That’s the number one reason for going to the larger wafer sizes,” Chiang states.

“In the past, our competitors were UMC, SMIC and others that were much smaller than us. So by promoting 300-mm wafers, we took advantage of them. But when going to 450 mm, we only have two competitors: Intel and Samsung. Both are bigger than we are. So the transition wouldn’t help us at all. It would actually hurt us,” Chiang continues.

450mm wafer
A Molecular Imprints engineer holding up a patterned 450-mm wafer. The US developer of nanoimprint lithography equipment considered 450 mm to be an opportunity to squeeze into the semiconductor ecosystem. Credit: Molecular Imprints

Underestimated

It was no secret that semiconductor equipment vendors, including ASML, were by no means eager to develop 450-mm systems. They’d coughed up 12 billion dollars to develop 300-mm equipment, according to estimates by VLSI Research, and they complained that they’d seen very little return on that investment. They weren’t going to let that happen again, especially given the fact that the next transition would be much more expensive – up to 100 billion dollars, according to some estimates.

“I never liked 450 mm, I’ve never kept quiet about that. Not even to customers. No one has ever been able to convince me that it would bring cost savings,” ASML CTO Martin van den Brink told Bits&Chips in early 2014 (link in Dutch).

In lithography, there’s no obvious advantage to larger wafers sizes, since scanners expose one small section at a time and therefore larger wafers take longer to pattern. Thus, to process a 300 and a 450-millimeter wafer in the same amount of time, the processing speed per unit area has to go up, while in principle, it goes down because larger and heavier wafers are being handled. But what would be ASML’s incentive to maintain the throughput? Since customers would need to buy fewer scanners, would they be willing to pay proportionately more for the 450-millimeter systems?

Moreover, at the time, ASML already had its hands full with the development of EUV scanners, which was proceeding much more slowly than originally planned. A set of alpha tools had been developed relatively quickly at the start of the century, but soon after, the Veldhoven-based company began to realize that it had vastly underestimated the industrialization of the technology. It would very much prefer to have every available engineer working on EUV.

Great optics

As one of the key players, ASML didn’t start 450-mm development until customers were willing to help pay for it. In July 2012, Intel took a 2.5-billion-euro, 15-percent stake in the equipment manufacturer and also put up 830 million euros in R&D money, of which more than 550 million was earmarked for the development of 450-millimeter equipment. TSMC (five percent stake and 276 million euros) followed soon, as did Samsung (3 percent and 276 million).

Earlier, in 2008, the big three had announced that they would work together to get 450 mm off the ground. In 2011, together with IBM and Globalfoundries, they launched the Global 450 Consortium (G450C) to start developing a 450-mm ecosystem. Notably, Nikon, which had Intel as its largest customer, delivered the only optical 450-millimeter scanner ever made. Around 2011-2012, the first plans for 450-millimeter fabs also came out.

“As a market leader, you can’t just say no to your biggest customers. You can have an opinion about it, you can challenge them to convince you, but in the end, you have to accommodate them,” Van den Brink said about the reluctance with which ASML began work on 450 mm after Intel, TSMC and Samsung had wired the money.

Then, during a keynote speech at the International Solid-State Circuits Conference (ISSCC) in early 2013, Van den Brink revealed that ASML had committed to the same processing speed per wafer area unit. So, in the lithography domain, chipmakers wouldn’t get a productivity improvement, but they claimed that they would make up for that in the rest of the production process, in which the processing speed of most steps is (almost) independent of wafer area.

Van den Brink said something else of note at that ISSCC. While it was generally assumed that the die was cast on 450 mm now that G450C had been established and Intel, Samsung and TSMC were co-paying, the ASML CTO observed that industry enthusiasm for it was still underwhelming.

Less than a month later, Chiang walked into Chang’s office to talk him out of moving to the larger wafer size. Chang realized his COO was right, called several internal company meetings and consulted the other major chip machine manufacturers Applied Materials, KLA-Tencor and Lam Research, who indeed had no appetite for 450 mm. Now, TSMC needed a good excuse, since reversing course on a technology you touted doesn’t have great optics.

“It’s not off the table, but I expect it to be pushed out at least two years,” Van den Brink said in 2014, adding that he didn’t rule out 450 mm would never be resuscitated. G450C was quietly buried in 2017. Today, TSMC’s market capitalization is 465 billion dollars, while Intel’s is 150 billion dollars.

Main picture credit: TSMC