TSMC’s plans for N2 include backside power delivery

TSMC has unveiled new details about its 2nm IC family, of which the first member is scheduled to enter production in 2025. Its first node to feature gate-all-around transistors, the foundry says N2 will combine a density gain of roughly 15 percent with a 25-30 percent power reduction at the same speed compared to N3E – the still-to-be-introduced relaxed version of the original N3 (or N3B) process that entered production in H2 2022.

In 2026, TSMC plans to introduce the N2P process featuring backside power delivery. BPD moves power wires underneath the transistor layer, at the backside of the wafer. This reduces clutter in already overcrowded metal layers, enhances signal integrity and delivers density and power performance benefits. Pioneered by Imec, Intel also has its own version of BPD lined up for its 2nm-equivalent node.