Though recently developed prototypes still consist of 50 qubits maximum, Delft startup Qblox is paving the way for building quantum computers with up to a 1,000 qubits and beyond.
Affordable phased arrays, built using low-cost silicon chips, have become an essential technology for high-data-rate terrestrial (5G) and satellite (satcom) systems because of their high gain, electronically steerable patterns, narrow beam widths, high tolerance to interference and adaptive nulling capabilities. They have also become the backbone of all LEO and MEO satellites (non-geostationary), both at the payload level and at the user terminal. High-EIRP, high-performance systems at X, Ku and Ka-bands and 60 GHz with analog and digital beamforming capabilities and with multiple beams are now available at low cost due to the immense commercial investments placed in the past 5 years. These advances are reshaping our communication and radar/sensor systems, as we work to change our world from the Marconi era given by low-gain broadcast and user-terminal antennas to the directive communications era where every antenna, every beam, every sensor is electronically steered. This talk summarizes our work in this area and presents a roadmap for the future.
Gabriel Rebeiz is Member of the National Academy (elected for his work on phased arrays) and a Distinguished Professor and the Wireless Communications Industry Endowed Chair at the University of California, San Diego. He is an IEEE Fellow, and is the recipient of the IEEE MTT Microwave Prize (2000, 2014, 2020), all for phased arrays. His 2×2 and 4×4 RF beamforming architectures are now used by Renesas, ADI, NXP, Infineon, Sivers, Qualcomm, Intel, Samsung, Boeing and others, and most companies developing communication and radar systems. All satcom affordable phased arrays are based on his work and architectures.
Entrepreneurship is more hyped than ever, but many start companies with limited understanding of what is required to build a successful enterprise. Based on 30 years of experience in starting, advising and investing in companies, this talk shares 10 lessons that were learned the hard and costly way.
Jan Bosch is a professor of software engineering at Chalmers University of Technology in Gothenburg, Sweden, and director of the Software Center, a strategic collaboration between 17 large European companies (including Ericsson, Volvo Cars, Volvo Trucks, Saab Defense, Scania, Siemens and Bosch) and five universities focused on digitalization. He also holds a part-time position as professor of AI engineering at Eindhoven University of Technology, the Netherlands. He received a MSc degree from the University of Twente, the Netherlands, and a PhD degree from Lund University, Sweden. His research activities include digitalisation, evidence-based development, business ecosystems, artificial intelligence and machine/deep learning, software architecture, software product families and software variability management. In the startup space, he’s an angel investor in several startup companies.
With the shipment of its first system to a high-end chip manufacturer, Nearfield Instruments proves that the semiconductor market is very much open to innovative solutions for advanced process control metrology. This first product, Quadra, can measure in-line and in great detail (ångstroms) the on-surface high-aspect-ratio (10:1) features of integrated circuits. The company is now scaling up to deliver dozens of its scanning probe metrology systems per year.
Nearfield founder Hamed Sadeghian foresees the Quadra metrology platform to be the basis for several products and product lines. All of them will solve different problems the semiconductor industry is facing to follow Moore’s Law with its ever smaller and 3D features. Nearfield is expecting to deliver its second product line based on the Quadra platform next year. This system will be able to image, non-destructively, subsurface structures with nano-precision.
In this talk, Hamed Sadeghian will highlight the major requirements for developing non-destructive 3D high-volume manufacturing metrology equipment in the semiconductor industry, the architecture of Quadra (including software) and the challenges faced and overcome. He will also address the impact of the system architecture on the outsourcing strategy to the high-tech supply chain.
Hamed Sadeghian received his PhD (cum laude) in 2010 from Delft University of Technology. Four years later, he obtained an MBA degree from the Vlerick Business School in Belgium. He is the founder (2001) of Jahesh Poulad Co., a manufacturer of mechanical equipment.
Hamed was a principal scientist and Kruyt member of TNO and led a team of thirty researchers in nano-optomechatronic instrumentation at TNO in Delft from 2011 to 2018. In 2016, he co-founded Nearfield Instruments and is currently CEO/CTO at this scale-up that recently shipped its first in-line metrology system to a high-end chip manufacturer.
In the automotive industry, Aspice is used for measuring an organization’s capability to develop high-quality software. Companies supplying software to automotive manufacturers are required to have a minimum maturity level to ensure that they deliver that high quality. Still, having high-quality processes in place and complying with them is no guarantee. To see why that is and what else is needed to assure high quality software, we first need to understand the many different aspects of software quality and the influence they have. In this talk, Ger Cloudt will present a holistic view on software quality using the 1+3 SQM approach, addressing the consequences of high or low quality for each of the four defined quality types.
Since the beginning of 2019, Arjen van Elteren is lead software architect at Nearfield Instruments. From 2009-2019, he worked as a senior software engineer/architect for the Leiden Observatory . Before that, he was as a software engineer atcompanies such as ASM and HP.
The Dutch high-tech equipment builders are all leaders in their markets, owing to their strength to handle the complexity of the systems they create. This talk will discuss how the industry must now prepare for the next levels of complexity, as their systems are getting integrated in complex workflows (effectively becoming systems-of-systems), are including more and more AI and are becoming subject to continuous upgrades. This calls for a new generation of methodologies and ways-of-working, like MBSE (model-based systems engineering) and open-source tooling. In addition, it calls for quickly getting a new generation of engineers up to speed, moving from intricate and outdated documentation to models as means to quickly capture and share the essence of complex systems. And finally, it raises the question how to educate the next generation of engineers to equip them with the systems thinking skills needed to deal with this next generation of complexity.
Wouter Leibbrandt is science and operations director of ESI (TNO). Before joining ESI in 2016, he was with NXP Semiconductors for 10 years, where he managed the Advanced Applications Lab.
Imagine a system that, once turned on, will stay operational for the rest of its life. Hardware parts may break or go obsolete, software components may crash, cyber attacks are part of everyday life and knowledge of the system itself becomes volatile. Critical systems in general are software intensive and have life times of 30 years and longer. Just imagine how such systems should be designed and what challenges we have to conquer. Together with partners, Thales has developed an open architecture (Inaetics) in 2016 that addresses these challenges. Today, a number of areas for improvements have been identified and put on the agenda for the Inaetics Extended project. This talk will present the challenges we need to conquer.
René van Hees worked for several software companies in both the Netherlands and Germany before he started at Thales Netherlands in 2002. In his role of chief software architect, he is responsible for all technological, process, methodology, architectural and innovation-related aspects concerning the development of (real-time embedded) radar sensor software.
What does this part of my software do? How does it behave in different situations? And why does a software change cause a regression in a seemingly unrelated part of my system? Understanding software behavior is becoming more and more essential to handle the complexity of high-tech systems. ESI developed and applied model inference to automatically obtain software behavior models that provide valuable insights. These models can be compared to quickly determine the impact of software changes on the system behavior, and locate potential regressions before the software is deployed. How can this help you?
Dennis Hendriks is a senior research fellow at ESI and a part-time researcher at the Radboud University Nijmegen. His research area is software behavior. He makes academic formal methods ready for industrial use through applied research, bringing academia and industry together for win-win collaboration and creating real impact together.
At Nexperia ITEC, we already have a 30+ years history in back-end assembly equipment development. This has resulted in a significant large and complex codebase. In the dynamic development environment of ITEC, we started rejuvenating our codebase for more efficient and structured code development. For this, we have started a partnership with ESI in the Bright program. One of the goals is to rejuvenate our codebase by applying innovative tooling to support the software refactoring tasks. This talk will present the activity of automatically transferring visual inspections integrated in the Adat die bonder software application. Since there are many instances of visual inspection tasks connected up to 14 camera positions in this system, the main challenge was to run data-driven code analysis to learn the specific instance of inspection calls in the application. By doing automatic transformations, a serious development speed-up, an improved code quality and a more maintainable code base have been achieved.
Raymond Rosmalen has more than 20 years of experience in the field of machine vision. He studied physics at the Radboud University in Nijmegen and did his PhD on high-energy physics contributing to the LEP experiment at CERN. Currently, he is the machine vision technology architect at ITEC. ITEC develops back-end semiconductor assembly equipment with integrated and standalone machine vision solutions. The main challenge is the increasing quality inspection criteria combined with the increasing system speed requirements to achieve lowest cost of ownership. This requires highly efficient and optimized inspection solutions and a continuous drive to explore new vision technologies.
Reasoning from the symptoms towards the cause of an unwanted behavior (diagnostics) of a complex high-tech system is a difficult brain teaser – potentially a very expensive one: every minute matters. This talk presents an hybrid AI framework, developed in collaboration with Canon Production Printing, that combines machine data, models derived from the system’s design and optimal tests to quickly pinpoint the most likely cause of the system malfunction. It also sketches how this approach can evolve into predictive maintenance.
Leonardo Barbini is a research fellow at ESI working in the areas of probabilistic reasoning and knowledge engineering for diagnostics and prognostics of high-tech systems. His main research interest is developing a set of computational tools that allow humans to quicker resolve machine problems.
Emile van Gerwen is a research fellow at ESI. He has a strong industrial background in software-centric high-tech systems. His passion is bringing mathematical sound principles into the jungle of practical system engineering. The areas he worked in include probabilistic decision support systems, error-free event-driven control software and diagnostic reasoners that combine design knowledge with machine sensor data.
To keep your competitive edge, you need to innovate, which means to transform your organization to adopt new technologies to perform better in the end. In practice, this is very challenging. What is the added value of the new technology? What processes do you need to create or adapt to capture this added value? What is the impact on your teams and their required skills and mindsets? These are three major questions that you need to address when considering new technology to improve business. At Thermo Fisher Scientific, we are working on using model-based testing techniques to manage the complexity of developing, testing and maintaining the interfaces between software components. These techniques enable via modeling the automatic generation and execution of test cases. At ICT, we are supporting Thermo Fisher Scientific in adopting these new techniques. Thermo Fisher Scientific is a large organization, their software is complex, their market is highly competitive and their customers highly demanding. This talk explains how ICT and Thermo Fisher Scientific are answering the three major questions above. At the end, the main question remains: how do we effectively explore and discover the added value of a technology like model-based testing, the processes and the skills required to succeed?
Julien Schmaltz is a principal consultant at ICT Group guiding customers in the digitalization of their software engineering process. He holds a PhD degree in electrical engineering from the University of Grenoble, France. Before joining ICT, he was an associate professor in computer science at Eindhoven University of Technology conducting research and education in the field of model-driven engineering with applications to hardware and software systems. Together with universities, he is actively engaged in facilitating the transfer of technology created by academic research to the market through cooperation with students and spin-off companies.
Arjen Klomp is responsible for software technology, integration and test at Thermo Fisher Scientific in Eindhoven. He joined the company in 2017. After his graduation in computer science from the University of Twente, he had various roles in software development, starting as a developer and then growing into architecture and technical leadership roles. In these roles, he worked on a variety of products ranging from high-volume consumer products to low-volume high-tech products. The common thread always was and is to find innovative and better ways to develop software, either with new technologies or quickly adopting new ways of working.
Many AI/ML/DL projects fail to go beyond the experimentation and prototyping phase. Successful deployment of ML/DL models in large systems requires AI engineering. This talk presents an overview of what else is needed to deploy ML/DL models in production-quality, industry-strength systems.
Jan Bosch is a professor of software engineering at Chalmers University of Technology in Gothenburg, Sweden, and director of the Software Center, a strategic collaboration between 17 large European companies (including Ericsson, Volvo Cars, Volvo Trucks, Saab Defense, Scania, Siemens and Bosch) and five universities focused on digitalization. He also holds a part-time position as professor of AI engineering at Eindhoven University of Technology, the Netherlands. He received a MSc degree from the University of Twente, the Netherlands, and a PhD degree from Lund University, Sweden. His research activities include digitalisation, evidence-based development, business ecosystems, artificial intelligence and machine/deep learning, software architecture, software product families and software variability management. In the startup space, he’s an angel investor in several startup companies.
Easics’ NearbAI technology allows you to configure and optimize a semiconductor IP core that performs real-time low-latency low-power neural network inference in a small package. It is platform-independent both in the way you train and capture your neural networks and in the hardware component on which you map the IP core. This talk will compare the performance between two FPGA targets and one ASIC target of the same neural network implemented using NearbAI.
Ramses Valvekens is managing director of Easics since the management buy-out in 2004. Besides his role as CSO, active in the NearbAI product line of low-latency embedded neural network inference engines, he also takes up a system architect role, focusing on technology selection, project risk reduction and cost-effective mixed-signal ASIC and FPGA design trade-offs. He holds a master’s degree in electronics engineering from the Katholieke Universiteit Leuven, performed research at Grenoble INP and was a research scholar at Lawrence Livermore National Laboratories in California. He is co-inventor of two telecom patents.
To move quantum computers from the proof-of-principle stage towards real-life applications, many engineering challenges need to be overcome. Amongst these are the generation and routing of control signals. As most of the platforms require signal frequencies between DC and 20 GHz, these challenges are for a large part RF engineering challenges. The fundamentally sensitive nature of qubits drastically complicates these: qubits need to be placed at ultralow temperatures (<< 1 K) and control signals require extremely precise timings (<< 1 ns), low signal noise, distortion, drift and crosstalk. Qblox and Delft Circuits work precisely on these topics and provide quantum computer developers around the world with their state-of-the-art control technology. This talk starts at the level of the quantum bits to understand their control needs at a fundamental level and goes up into the stack layer by layer to discuss challenges in the cabling (Delft Circuits), the control electronics (Qblox) and the digital infrastructure for feedback (Qblox).
Niels Bultink specializes in controlling quantum computers, performing the first feedback on solid-state qubits in 2012. His PhD research with Leonardo DiCarlo at Delft University of Technology has led to more than ten scientific publications centered around fault-tolerant quantum computing with superconducting circuits. The work at Qutech enabled the control of setups with up to 50 qubits and has now found its way to the market via the company Qblox. With Qblox’s new and industrialized generation of control stacks, he is paving the way for quantum computer integrators worldwide to reach practical applications in quantum computing.
Daan Kuitenbrouwer has a background in physics and innovation management. After his master’s, he co-founded Delft Circuits and started in a technical role developing the product. Later, he shifted his focus to operations, business development and sales. Within his job, he combines a thorough understanding of building companies and their operation in larger ecosystems with his background in physics. As such, he is also one of the leaders of the Impaqt consortium, where multiple quantum supply companies collaborate to build a quantum system.
Intelligent sensing will be central in providing a seamless user experience in electronic devices – headphones that understand the difference between speech and background noise, security cameras that can differentiate between humans and pets, wearables that can detect if you’re falling ill. However, the narrow power envelope of these battery-powered devices is often a significant obstacle in realizing rich application functionalities based on traditional neural networks. Innatera employs a radically different approach to processing data efficiently at the sensor edge. Using brain-inspired spiking neural networks atop a programmable analog-mixed signal architecture, Innatera’s spiking neural processor enables always-on sensing applications within an ultra-low power budget. This talk introduces the spiking neural processor and outlines how its neuromorphic architecture enables sub-milliwatt signal processing and pattern recognition at the sensor edge.
Sumeet Kumar is the CEO of Innatera Nanosystems, the pioneering Dutch neuromorphic processor company. He holds an MSc and PhD in microelectronics from Delft University of Technology, the Netherlands. He was previously with Intel, where he worked with the Imaging and Camera Technologies Group developing domain-specific tools for the development of complex media processor architectures. At Delft, he is credited with creating two highly successful European R&D programs developing energy-efficient compute hardware for highly automated vehicles, together with organizations including Infineon, NXP and BMW, among others. He was also responsible for leading industry-focused research on power-efficient multiprocessors and computational neuroscience.
In 2005, when Iris Soute together with two fellow students designed an outdoor, interactive game based on the board game “Colonists of Catan,” she never imagined that this small project would grow out into a company selling a product worldwide. This talk will take you along the path that she followed, from the duct-taped prototype to Picoo today.
Iris Soute is the inventor and co-founder of Picoo. Originally trained as a mechanical engineer, she worked for 3 years at Philips as a software engineer. Then she returned to the university to study user interaction design, followed by a PhD in industrial design. Picoo is the result of Soute’s PhD research into interactive gaming solutions for children. Currently, she is CEO of Picoo; she manages general affairs and is responsible for game design, strategic planning and customer relations.
You want to stay ahead of your competitors by bringing the best product to the market, at the right time and at the right price point. Developing your own custom chip (ASIC) could be the best strategy for you. With one single-chip implementation, you could boost computational performance, massively cut power consumption and product size, and reduce unit cost. Moreover, ASICs are very difficult to copy, so protecting your IP is relatively straightforward. Despite these obvious advantages, creating an ASIC is often perceived as a difficult process – with development cost and time as the main hurdles. This talk will demonstrate that this perception is often no longer valid. ASIC development is well within reach for many companies, even if they’re not yet acquainted with the process. As director of business development at Imec.IC-link, Bas Dorren will talk from his experience of managing many ASIC projects in a wide range of technologies for a large customer base worldwide. He will explain what it takes to make an ASIC in terms of knowledge, cost and time. And he will make clear what the benefits could be for you.
Bas Dorren spent more than 20 years in various technical and commercial roles of several semiconductor companies. More than 10 years ago, he joined Imec.IC-link, Imec’s ASIC services group. Currently, he manages the business development activities. His team provides flexible turnkey ASIC services, including ASIC development and supply chain services to startups, SMEs and established OEMs, as well as universities, IC design houses and system companies. Dorren holds an MSc degree in physics from Utrecht University and a PhD degree in physics from Eindhoven University of Technology.
Developing innovative high-tech equipment is a daunting challenge, especially for startups and scale-ups. Solid systems engineering and lots of organizing are required when working with partners from different fields of expertise (which is almost always the case). Generating new ideas and validating them in your next prototype can take a lot of time. And there is always the risk of drowning in specifications, procedures and organizational issues. But your engineers want to engineer! The solution? Do it Agile! Surprisingly, an Agile approach with short development cycles will also work in high-tech development. The key is taking smaller steps, dividing the components into really small functional units, which can be either software, programmable logic, electronics or mechanics. Next, project partners quickly build and develop these units in a parallel process or they can employ third parties such as prototyping services to do this. Finally, hardware and software units are integrated into a working prototype, ready to be tested. This way, the short cycles generate quick and frequent feedback on product feasibility. With an Agile approach to high-tech development, it becomes much easier to keep the focus on the technical development of the next prototype. It allows all partners to concentrate on building the best possible components. This talk will highlight the advantages of Agile high-tech development, using as an example real-life cases, such as the development of crucial components for a multi-beam scanning electron microscope.
Remco Jager is a project manager at Technolution Advance, a company that supports startups, scale-ups, and leading innovative manufacturers to bring advanced, innovative ideas to market quickly. Building upon 18 years of experience with the development of solutions for the semiconductor industry, Jager realizes cutting-edge innovations for a wide range of customers in high tech. He has a broad and detailed technical understanding and a talent for creating overview and shaping processes.
Surfix Diagnostics is an early scale-up, bringing biosensors based on integrated photonics to the market. In this talk, CEO Maarten Buijs will try to convey what lessons he has learned during his corporate career on how to bring deep-tech innovations to the market, and how to apply them to the challenges Surfix is facing.
After drafting the roadmap for biosensors based on integrated photonics for Photondelta in 2020, Maarten Buijs is now the CEO of Surfix Diagnostics. Before engaging with integrated photonics, he was responsible for R&D at FEI in Europe (presently Thermo Fisher Scientific), ASML EUV, Nucletron/Elekta and finally Moba. Prior to that, he worked for 14 years at the Philips Natlab.
Although we don’t know exactly how wireless communications will look like beyond 2030, we may assume that we will most likely communicate using holograms and digital twins, and that the merge of real and virtual reality has happen in an hyper-reality internet. Such new ways of communications will demand a large capacity and ultra-low latency. Developing technologies to exploit the terahertz frequency spectrum to implement terabit data capacity wireless links seems a futuristic endeavor. This talk considers the role of photonics in tackling the challenge to realize systems to generate, detect, multiplex and process terabit volumes of data in wireless terahertz systems.
Idelfonso Tafur Monroy is a professor at the Department of Electrical Engineering of Eindhoven University of Technology. He is a principal investigator in the Center for Quantum Materials and Technology Eindhoven (QTE), the Institute for Photonics Integration (IPI) and the Center for Wireless Technology (CWTE) and co-founder of the Center for Terahertz Science and Technology (CTSTE). He performs and supervises research on the convergence of electronics and photonics technologies for applications such as THz communications, sensing and imaging. More recently, he and his team are setting up the Eindhoven test bed for quantum secure communications, as part of the national Dutch program Quantum Delta.
The promises of 1Gb/s+ cellular data connectivity made by 5G network roll-outs is confronting fixed network operators with the risk of being left behind. As a consequence, the capability of an operator to offer a stable, affordable and ubiquitous 1 Gb/s internet connection is now no longer considered the holy grail but the next step needed to stay competitive. Early deep-fiber roll-outs show that high customer interest and retention are not enough to build a viable business with nation-wide availability, even when wireline technology is used for the final curb to home connection. By introducing wireless CMOS mm-wave technology in the network, a more favorable split between up-front and at-signup installation cost is achieved and a much wider range of neighborhoods can be serviced. This talk presents some of the technologies and methodologies used to build a carrier-grade 60 GHz product for the fixed-wireless access market with a fully integrated CMOS transceiver phased-array IC at its core.
After obtaining his MSc and PhD at KU Leuven, Carl De Ranter began his career at RF Magic, an RFIC Startup in San Diego, CA. There he worked on terrestrial and satellite TV tuners and became design manager to help build the start-up ahead of its merger and IPO. In 2013, he returned to Belgium to join design services house Ansem where he architected NFC and RFID front-ends. From 2015-2019, he consulted for a tier-1 smartphone chip supplier where he built the team that developed front-end RFIC IP shipping in over 100 million mobile phones. In 2019, he co-founded Pharrowtech, an Imec spin-off that develops mm-wave CMOS radio hardware and software for next-generation wireless applications.
While 5G is being rolled out, 6G is already on the horizon to further increase wireless data rates up to 100 Gb/s for new applications such as 3D holography. These high data rates are best accommodated in wide frequency bands above 100 GHz, such as the D-band (110-170 GHz). So far, the functionality of wireless transceivers has been mainly implemented using downscaled CMOS, which allows a high integration complexity while featuring very fast transistors. Today we have come to a point where CMOS downscaling no longer increases transistor speed. In combination with the low supply voltage of nanoscale CMOS, generation of power, especially at mm-wave frequencies, is challenging for CMOS. To generate sufficient transmit power, D-band transceivers will need to resort to non-CMOS technologies such as InP. This talk will discuss how the combination of the antenna array, required for beamforming, the active circuits from different IC technologies (CMOS and InP) and advanced 2.5D or 3D technology can result in a high-performance 6G wireless transceiver.
Mark Ingels received the MSc and PhD degrees in microelectronics from the ESAT-MICAS Laboratories of the KU Leuven in 1990 and 2000, respectively. In 1999, he joined Alcatel Microelectronics, which was later acquired by STMicroelectronics, and worked on the integration of ADSL analog front-ends and Bluetooth RF transceivers. He joined Imec in 2005 and is now a principal member of technical staff in the Advanced RF research group working on mm-wave transceivers for future communication systems.
5G/6G wireless communication data bandwidth will get a large boost when we can efficiently exploit mm-wave and sub-THz frequencies that allow us to transmit over large contiguous bandwidths. To transmit at these carrier frequencies, engineers use active antenna arrays with beam steering to overcome the high path loss. Testing and validating these actively steered antenna arrays and beam steering algorithms is complex and expensive, often involving large chambers and over-the-air (OTA) measurements. This talk provides an overview of the different validation and test options for mm-wave active antenna array modules and related research and technology challenges. It will present NI’s current innovation activities around OTA measurements and discuss potential solutions to many of the challenges, enabling lower cost and thus broader adoption of the 5G/6G frequency bands.
In 1990, Marc Vanden Bossche received the PhD degree from Vrije Universiteit Brussel in electrical engineering focusing on the foundation of high-frequency large-signal network analysis. In 1991, he established a Hewlett-Packard R&D team in Belgium continuing to work on characterization and system-level modeling tools for high-frequency non-linear electrical components, leading to the expansion of the capabilities of VNAs beyond S-parameters. In collaboration with NIST, a phase calibration standard was established in the second half of the 90s, merging network and signal analysis. In June 2003, Vanden Bossche founded NMDG, which was acquired by NI in October 2012. At NI, he and his team introduced vector calibration techniques into the NI RF production test systems. Presently, he is technically leading the accurate characterization effort under modulation conditions at NI and scaling these efforts for over-the-air characterization.
This talk will discuss the architecture of state-of-the-art load pull measurement systems for 5G and 6G applications. It will highlight the challenges involved in characterizing devices, circuits and systems for next-generation wireless applications, which pose very stringent requirements in terms of in-band (eg EVM) and out-of-band (eg ACPR) distortion. Application examples will be presented, including high-speed load pull for technology evaluations and power amplifier design, and modulated testing for 5G applications. Finally, a procedure will be described for evaluating traceable uncertainty in load pull measurements.
Mauro Marchetti received the BSc degree (cum laude) and the MSc degree (cum laude) in electrical engineering from the University of Naples “Federico II,” Naples, Italy, in 2004 and 2006, respectively, and the PhD degree from Delft University of Technology, Delft, the Netherlands, in 2013. In 2006, he joined the Electronics Research Laboratory at TU Delft where he carried out his PhD research on the development of advanced characterization setups for RF high-power and high-linearity amplifier design. In 2010, he co-founded and was appointed CEO of Anteverta, a company providing pioneering solutions in the fields of device characterization and high-performance power amplifier design. In 2015, Anteverta was acquired and became part of Maury Microwave. His research interests include the development of advanced characterization setups for RF high-power and high-linearity amplifier design.
The fast and ever-increasing demand for high-speed data services has been motivating and leading to define the next generation of telecommunication systems. To take advantage of this opportunity, methods and techniques to design RF and MW subsystems must continue to evolve to meet the requirements that include spectral and energy efficiency and, on the other hand, to reduce costs and time to market. To deal with these challenges, important works have focused on modeling and simulating front-end designs to allow analysis and optimization at a system level. This talk will present a comprehensive methodology to extract a black-box model of a power amplifier for two application examples: the evaluation of linearization techniques and the front-end design of an advanced antenna system.
Wissam Saabe is an application engineer at Amcad Engineering. He received the Master Research degree in electronics and optics for telecommunication from the University of Limoges in France in 2013, and is currently working towards the PhD degree at the Research Institute on Microwave and Optical Communications XLIM, University of Limoges. His research interests are non-linear analysis and behavioral modeling of RF and microwave circuits and subsystems.
Millimeter and sub-millimeter waves are nowadays being widely adopted within a variety of applications developed across the high-tech industry, including high-resolution automotive radar sensors, but also the fifth and sixth generation mobile communications RF front-ends. These applications primarily consist of a system-in-package tightly integrated with radiating elements to ensure adequate electromagnetic performance. Managing the design of such devices is particularly challenging from a manufacturing capabilities and related tolerances point of view, as the size of the metallic features shrinks with the frequency increase, but also due to the fact the power densities significantly increase, potentially leading to thermal issues. As such, RF IC package engineers not only need to accurately predict the electromagnetic performance of their implementation but also need to assess adequate thermal dissipation of these complex devices starting from early phases, driving their decisions towards the best system-in-package design sign-off. This talk will showcase solutions aimed at addressing these multiphysics simulation needs.
Anowar Masud received the BSc degree in electrical engineering from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1996, the MSc degree in electrical communication engineering from the University of Gävle, Sweden, in 2001, and the PhD degree in high-frequency electronics from Chalmers University of Technology, Gothenburg, Sweden, in 2008. He has more than a decade of working experience in the RF/antenna and microwave domains, especially in front-end IC packaging solutions, modeling and characterization. He initially worked as a circuit designer for specialized receivers with Ericsson and then joined Ansys in 2017 as a senior application engineer.
Although we have been developing RF power amplifiers for more than a decade, it does not grow old and the challenges remain. This talk will take you through the paces of a Doherty amplifier development process with all its pitfalls and hurdles. Using newly developed GaN devices as example, the flow will be illustrated step by step, sharing experiences in designing these amplifiers for 5G basestation applications in the 3.5 GHz band.
Martijn Brethouwer is a senior RF application engineer at Bruco Integrated Circuits. He has more than four years of experience in developing Doherty amplifiers. Before joining Bruco IC, he worked two years at Astron as an RF engineer. He holds an MSc degree in electrical engineering from the University of Twente.
With the current roll-out of 5G telecommunication infrastructure systems and especially with the new massive MIMO architecture and the opening of the higher sub-6 GHz frequency bands, the RF power amplifier architecture and technology have gone through a major transformation. The roll-out fueled and accelerated the technology developments and large advancements have been made at all levels such as power efficiency, linearity, bandwidth and integration. However, the next and future steps in 5G LTE networks, necessary to fulfil the growing demand of wireless communication, prove to be even more challenging. This talk sketches the progress that has been made so far, as well as the future trends and challenges from an RF power amplifier point of view.
Fred van Rijs holds a PhD in electrical engineering from Delft University of Technology. In 1992, he started at Philips Research Laboratories in Eindhoven on advanced silicon technologies such as SiGe HBTs. In 1999, he moved to Philips Semiconductors in Nijmegen, later NXP Semiconductors, initiating pHEMT technology for the next-generation CATV linear power amplifiers and was responsible for the development of LDMOS technology for base station RF power amplifiers. Currently, he is working at Ampleon on technologies required for future RF power applications.
There’s no denying that cloud computing has been a top technology over the past two decades. So many of us working from home since the start of the pandemic would have been impossible not that long ago. Even though the cloud is key for today, it can’t handle the technologies of the future. Self-driving cars are a perfect example. They need to make ultra-fast, perfectly accurate decisions. There’s no time to wait for data to be processed in a data center. This is where edge computing comes in. Edge computing cuts across the IoT – from home and work to the most complex of all, the vehicle. Coupled with the rising digitalization that leads to everything connected, high-performance edge compute platforms are transforming ecosystems and the development landscape. In this talk, Maarten Dirkzwager will share why mastering edge computing with the right level of safety and security is critical to enabling next-generation technologies.
Maarten Dirkzwager is responsible for corporate strategy and chief of staff to the NXP management team. He joined the company in 1996 at Philips. After several roles in central engineering, he moved to Philips Semiconductors in Hong Kong in 2005, where he was responsible for the innovation, efficiency and strategy of the discrete back-end factories. In 2009, he moved to the corporate strategy team in the Netherlands where he was involved in the transition of NXP to a profitable high-performance mixed-signal player. In 2015, he played a leading role in NXP’s acquisition and integration of Freescale, which resulted in creating one of the leading semiconductor companies and a leader in automotive semiconductors. In 2017 and 2018, he worked as head of strategy for ASML and AMS, after which he returned to NXP in early 2019.
