Blurring boundaries in chip manufacturing

Those of us not yet retired are going to witness it with great certainty: the end of chip scaling as we know it with the current lithography tools. In roughly a decade, we’ll end up in sub-nanometer structures. The discussion about the lithography tool at that time – high NA, hyper NA or some other turbo variant of EUV – won’t really matter. The semiconductor industry will opt for the cheapest path to continue to make progress and manufacture chips reliably and quickly. Whatever tools IC process engineers will use, we’re going to feel the physical limits in the coming ten years.

The interesting thing is that everyone in semicon seems to agree that Moore’s law will continue for a while after that. The semiconductor roadmap is truly bursting with technology as well as ideas to keep up the steady rhythm of more devices on the same chip surface. System architects will use the available silicon surface more efficiently. They already have techniques at their disposal to guarantee atomic sharpness and exploit the third dimension.