EUV needs a couple more years to fully mature

When TSMC introduced EUV lithography into high-volume semiconductor manufacturing last year, it did so cautiously. In a bid to reduce the usage of multipatterning, the so-called N7+ process featured up to four EUV-patterned layers. For its successor, the N5 node, that number goes up to a maximum of 14 layers. By mid-2022, when production of the 3nm node (N3) will get into full swing, over 20 layers per chip will be printed with an EUV scanner, ASML CEO Peter Wennink recently told investors (without mentioning TSMC specifically).

How is TSMC going to print all those layers? Well, installing a lot of machines is one way to go. Already, the Taiwanese foundry says that it has half of the world’s EUV tools in operation and according to Digitimes, the company just put in an order for 13 more. As fab floor space is extremely expensive, though, TSMC and other leading-edge chipmakers prefer to install as few EUV scanners as possible. They’d rather buy machines that process more wafers per hour, day or week.