Imec showcases high-NA EUV patterning abilities

Imec has released several images of single-exposure patterns that demonstrate the imaging capabilities of ASML’s high-NA EUV scanner. Demonstrating logic structures down to a 9.5nm half-pitch, 30nm center-to-center random vias and a DRAM-relevant pattern at P22nm pitch, the results “confirm the readiness of the ecosystem to enable single exposure high resolution high-NA EUV lithography,” Imec says.

The patterns were created at the ASML-Imec High NA EUV Lithography Lab in Veldhoven, where Imec and semiconductor manufacturers take turns getting to know the new-and-improved EUV scanner. Of course, patterning isn’t just about lithography. Deposition, etching, metrology and other processes all need to come together to create sharp images.

“We are thrilled to demonstrate the world’s first high-NA-enabled logic and memory patterning as an initial validation of industry applications. The results showcase the unique potential for High NA EUV to enable single-print imaging of aggressively-scaled 2D features, improving design flexibility as well as reducing patterning cost and complexity,” commented Steven Scheer, senior vicepresident of Compute Technologies&Systems/Compute System Scaling,

CEO Luc Van den hove added: “The results confirm the long-predicted resolution capability of high-NA EUV lithography, targeting sub-20nm pitch metal layers in one single exposure. High-NA EUV will therefore be highly instrumental to continue the dimensional scaling of logic and memory technologies, one of the key pillars to push the roadmaps deep into the angstrom era.”