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CMOS goes 3D
The future of CMOS scaling hinges on the industry finding ways to harness the third dimension, explains Imec’s VP Logic Technologies Julien Ryckaert.
Traditional scaling is hitting multiple walls at once as the main driver of Moore’s Law – lithography-based shrink – is losing steam. The benefits of going down the node ladder in terms of power and performance have been slowing down for over a decade now, while costs are going up. Meanwhile, memory bandwidth can’t keep up with processor performance, limiting overall system potential. And as if that’s not enough, it’s becoming increasingly challenging to bring power into the chip and extract the heat that’s being generated inside.
Still, the world’s foremost semiconductor research firm sees a way forward: Imec’s roadmap will take CMOS to the 0.2nm or A2 node by 2036, keeping an introductory pace of two to two-and-a-half years. How? The keyword is 3D. On the device level, transistors will eventually morph into three-dimensional entities, stacking NMOS and PMOS on top of each other. Chips themselves will turn into 3D assemblies as well, in which memory and logic are intimately arranged one upon the other.