It’s the manufacturing, stupid!

We use a lot of energy due to the widespread use of chips in various devices. Chips are basically everywhere except in toilet paper (although that may be an interesting idea). Together, these chips use significant energy, leading to a strong effort to reduce this power consumption. We want our batteries to last longer and our cloud servers not to suck up all our green energy. Thanks to Moore’s Law, on-chip features got smaller and distances shorter, so the energy per digital function exponentially decreased since the 1970s.

However, it’s predicted that this decrease in power consumption will soon level off. This means designing low-power chips, especially large digital chips, will become a challenge. One major obstacle in reducing power consumption is the interface between the processor and memory. Solutions like in-memory computing are therefore being explored.

In general, power consumption and chip area are inversely related for digital chips. One option is to create a small chip with a high clock rate and supply voltage, performing computations sequentially. Alternatively, a large chip with many cores running at a low supply voltage in parallel can be used, as this consumes less power. The latter approach is commonly employed in modern computing. Furthermore, by merging computing and memory into one large chip, the area increases, and power will be reduced.

There’s another aspect to consider: the energy required for chip manufacturing. The fabrication of chips requires electricity in the wafer fab, primarily for air treatments, which amounts to approximately 1.4 kWh per square centimeter of silicon produced. This energy requirement is expected to increase due to modern wafer scanners like ASML’s EUV monster, which consumes about a megawatt to produce 160 wafers per hour. Considering that a chip needs to go through twenty passes in such a scanner, this adds up to about 0.2 kWh in additional energy per square centimeter of the chip, giving a total of 1.6 kWh per square centimeter.

To put this into perspective, let’s take the area of a NiMH AA battery as an example. Its bottom measures approximately 1.8 square centimeters, while the battery contains 2,500 mAh of charge at 1.2 volts. 940 of such batteries placed on top of each other would contain the fab energy needed to produce the silicon area underneath. This stack would be 47 meters high!

Now let’s consider the chips in a smartphone. A typical smartphone battery has a capacity of 10 watt-hours. If we assume that 50 percent of that capacity is used every day to be dissipated in the chips of the phone, and multiply that by the number of use days during three years (the average lifespan of a phone), the total lifetime chip energy dissipation of the phone would be 5.5 kWh.

With that amount of energy, we can produce 3.4 square centimeters of silicon. A phone contains more silicon area than that, especially in its memory. But there’s more. The 1.6 kWh per square centimeter was only the wall plug power in the fab for chip production. The energy used to produce the materials before entering the fab and the energy used for packaging and shipping to customers should also be accounted for.

So, for battery-operated devices, the energy consumption during chip production far exceeds the lifetime energy consumption of the chips themselves. When we’re talking energy efficiency, the problem isn’t the energy use of the chips used in mobiles. If we want to save energy, we’d better focus on the manufacturing process.

Then again, a Tesla trip to the shop to pick up a new phone can easily take 5.5 kWh as well.