ASIC design in a reliable supply chain

Over the last few decades, driven by lower costs and higher volumes, there was a strong inclination to move the semiconductor supply chain to the Far East. Gradually, development and also R&D followed suit. Since 2019, the geopolitical winds have turned dramatically, and the importance of an independent semiconductor supply chain in the West is being acknowledged. How is a company like Bruco IC doing ASIC development in the Netherlands?

At Bruco IC, we’re delivering IC design services to a wide range of customers. These services can be divided into three types. The first is pure IC design. This involves IC design engineers who are assigned as additional resources to a customer’s design team.

The second type is IC development design. This means taking ownership of the full IC design up to GDSII with validation in close collaboration with the customer. The customer takes care of the wafer production, package assembly, test and qualification.

The third type is full turnkey ASIC projects, where we’re responsible for all steps from the IC design, validation and test program development, up to and including wafer production, package assembly, production test and supply to our OEM customers. An ASIC project requires strong collaboration with the customer, especially on application design, where the customer typically has the know-how.

Our typical ASIC customers are OEMs without an IC design team of their own, developing electronic applications with discrete electronic components. These OEMs can decide to go into production with a PCB, but when the volumes increase, or when very small sizes are required, the need for miniaturization arises, prompting the request for an ASIC. A typical ASIC development project can take 2-4 years and with several million euros in non-recurring engineering costs, it’s not a decision taken lightly.

Go/no go

The ASIC development process starts with a high-level feasibility assessment. This involves one of our system architects diving into the concept, performing some high-level modeling and determining which technology could be used, eg plain CMOS, BCD or SiGe. The outcome will be that, in principle, we can design the ASIC and that we have a clear idea of the process technology node to be used. The high-level feasibility assessment typically takes 2-3 months.

Once the customer accepts the outcome of the high-level feasibility assessment, an official feasibility study can be started. This phase includes the high-level IC requirement specification, the IP block specification, the IP block design and the IP block area definition, supported by a risk assessment. To meet the customer’s requirement for an early cost estimation, we need to assess the initial IC area, select the process, the foundry, the packaging partner and the assembly house and make a high-level project planning. Depending on the complexity of the ASIC, this phase takes 3-6 months, concluded by a report and passing the ATS milestone (Acceptance Type Study).

When choosing a production partner for an RF project requiring a 130nm SiGe process node, for example, the options include Globalfoundries and IHP in Germany and Israel-based Tower Semiconductor (part of Intel). For a 9×9-mm QFN64 package, we can go to Amkor or ASE with assembly in the Far East. The typically lower volumes of ASICs, however, aren’t interesting for these bigger companies, in which case Sencio’s functional packaging center in Nijmegen is a good alternative.

After ATS, next up is the definition phase, resulting in the ATD milestone (Acceptance Type Development). During this phase, further details are added to the IC requirement and IP block specifications and a more accurate IC area estimation is given, as well as a more accurate cost breakdown. At this point, the customer has all the information to make the go/no-go decision for the actual design. In parallel, design for test (DfT) is included to improve the testability. Salland Engineering in Zwolle is our preferred partner here. The definition phase can take between 3-4 months.

Silicon verification

Now it’s time for the real design work, with a team of IC design engineers, verification and validation engineers, an IC system architect and a project manager. They’re joined by a supply chain coordinator. A weekly project manager office (PMO) meeting safeguards the project’s progress.

The first part of the design phase takes between 6-12 months and is concluded with the AFM milestone (Approval for Mask Making). Here, typically, a multi-project wafer (MPW) is used, which is considerably cheaper than a full mask set. Wafer foundries have a quarterly run where customers can plan to join an MPW project with multiple different designs in one reticle. Such a run takes 6-8 months, delivering around 50-100 dies in a waffle pack.

The packaged samples are evaluated in the lab, using custom-made application boards that connect to the measurement equipment and measure the device according to the specification. Spec parameters are also tested at elevated temperatures. The validation results are summarized. Passing the SiV milestone (Silicon Verification) takes around 3 months.

Typically, the validation results in design improvements. These are implemented in the second part of the design phase, which is shorter than the first. The ensuing AFM2 milestone includes the final mask set ordering. A second silicon verification leads to the SiV2 milestone.

Qualification

In parallel, the characteristics of the silicon are measured using automatic test equipment (ATE). This starts with defining an electrical test specification based on the ASIC specification. Then, test hardware is developed and with the first functional samples, the electronics and software can be debugged. For qualification, ATE testing is key to comparing the measurement results before and after reliability testing and performing initial electrical failure analyses. Salland Engineering has been our partner here already for more than a decade.

Once the silicon has been validated on the ATE bench, we’re halfway through the ASIC development time path. Before we can release the product, we need to have it qualified and reach the RFS milestone (Release for Supply). We use two standards: JEDEC JESD 47 for consumer and industrial qualification and AEC-Q100 for automotive. Eurofins Maser in Enschede is our partner for the qualification tests.

Heterogeneous

A successful ASIC business is dependent on a reliable, predictable and trustworthy supply chain. Managing an unstable supply chain is a nightmare and especially the last couple of years have demonstrated challenges in capacity, price and lead time. At Bruco IC, we have partners all over the world. Because of all the interaction required, we work with flexible local suppliers as much as possible – in the same time zone, preferably nearby.

Within the Netherlands and Europe, we have a lot of semiconductor companies, ranging from design houses to fabless chip oufits, IDMs and OEMs. Wafer foundry services are a worldwide business. Although the US and EU Chip Acts might change this, our strength isn’t, and shouldn’t be, in mass production of single-digit nanometer process nodes but more in innovation and combining different types of technologies in one solution.

An illustrative example is the new Chip Tech Twente initiative of Kennispark Twente, the University of Twente and Twente-based companies, focusing on the development of heterogeneous systems based on photonics, semiconductors and assembly. The key is an open and transparent collaboration in a large partner network. As such, it’s likely to give our supply chain a boost as well.