Analysis

ASML puts peak litho rumors to rest

Paul van Gerven
Reading time: 3 minutes

Perhaps the number of exposures will peak one day, but it won’t be anytime soon, says ASML.

Whispers of semiconductor lithography being past its prime have haunted ASML over the past few months. “I think it’s time for investors to accept the decade of lithography is over,” investor blog Fabricated Knowledge wrote following ASML’s rather disappointing Q3 results. “Lithography spending will grow slower in the next decade than [the wafer fab equipment market overall].” According to a recent projection by Yole Group, WFE shipments (in dollars) are expected to grow with a 4.7-percent CAGR in the 2023-2029 timeframe. Not quite the double-digit growth rate ASML has grown accustomed to.

Naturally, ASML wanted to address these fears at its highly anticipated 2024 Investor Day, held on 14 November in Veldhoven. In fact, one could argue the entire afternoon was structured around debunking the peak lithography story, with most time dedicated to discussing EUV lithography. After all, if lithography intensity has peaked, that would show up first of all in EUV sales. Centering around the EUV theme may also have had the side-effect of steering away the conversation from China and export curbs, two intertwined topics that didn’t even come up for a change.

Shrink is still happening

CEO Christophe Fouquet, global head of corporate marketing Amit Harchandani and CFO Roger Dassen carefully laid out the argument in successive presentations. In short, it boils down to the expectation of electronics end-markets growing in the 2025-2030 period, translating into more bits and transistors being manufactured and ultimately more wafers being processed globally every year. Taking into account the composition of market segments, for example the share of leading-edge technology in the overall logic markets, and the evolution of semiconductor technology and manufacturing processes, for example featuring new transistor designs with different lithography requirements, this leads to an EUV-driven revenue increase of 10-20 percent CAGR for logic and 15-25 percent for DRAM. That’s well above Yole’s WFE market expectations.

Increasing wafer volumes (not shown) and growing number of EUV exposures per die drive strong growth of EUV scanner sales for both logic and DRAM manufacturing. Source: ASML presentation

At the heart of all this, of course, is the continuation of cost and performance benefits brought about by dimensional shrink. As argued by many chipmakers recently, the age of AI even demands a re-acceleration of Moore’s Law, of which shrink is still an important part. “Shrink is still happening. Neither logic customers nor DRAM customers have given up on shrinking. They’ll shrink as long as nothing stops them from doing that,” said Fouquet.

“The best way to shrink using a simple process is more EUV layers. When it comes to advanced logic and when it comes to DRAM, we’ll still see a significantly increased use of EUV node to node, year after year in both advanced logic and DRAM,” he added. So even if chipmakers will increasingly adopt non-litho-based patterning techniques going forward, lithography will prosper.

ASML projects system sales of 33-47 billion euros in 2030. The low end of this estimate amounts to a CAGR of 7 percent over 2024-2030 and the high end to 13.5 percent. So, all in all, ASML beats the overall WFE shipments as assessed by Yole. However, if you define peak litho as slowing growth rather than an actual decline in lithography intensity, there’s some merit to it: the CAGR of ASML’s overall sales over 2014-2023 was 16.7 percent.

Main picture credit: ASML

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